Datasheet ADCMP603 (Analog Devices) - 10

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ADCMP603 Data Sheet APPLICATIONS INFORMATION POWER/GROUND LAYOUT AND BYPASSING
This delay is measured to the 50% point for the supply in use; The ADCMP603 comparator is a very high speed device. Despite therefore, the fastest times are observed with the VCC supply at the low noise output stage, it is essential to use proper high speed 2.5 V, and larger values are observed when driving loads that design techniques to achieve the specified performance. Because switch at other levels. comparators are uncompensated amplifiers, feedback in any phase When duty cycle accuracy is critical, the logic being driven relationship is likely to cause oscillations or undesired hysteresis. Of should switch at 50% of VCC and load capacitance should be critical importance is the use of low impedance supply planes, minimized. When in doubt, it is best to power VCCO or the particularly the output supply plane (VCCO) and the ground plane entire device from the logic supply and rely on the input PSRR (GND). Individual supply planes are recommended as part of a and CMRR to reject noise. multilayer board. Providing the lowest inductance return path for Overdrive and input slew rate dispersions are not significantly switching currents ensures the best possible performance in the affected by output loading and VCC variations. target application. The TTL-/CMOS-compatible output stage is shown in the It is also important to adequately bypass the input and output simplified schematic diagram (Figure 14). Because of its supplies. Multiple high quality 0.01 μF bypass capacitors should inherent symmetry and generally good behavior, this output be placed as close as possible to each of the VCCI and VCCO supply stage is readily adaptable for driving various filters and other pins and should be connected to the GND plane with redundant unusual loads. vias. At least one of these should be placed to provide a physically short return path for output currents flowing back from ground
VLOGIC
to the VCCO pin. High frequency bypass capacitors should be carefully selected for minimum inductance and ESR. Parasitic
A1 Q1
layout inductance should also be strictly controlled to maximize the effectiveness of the bypass at high frequencies. If the input and output supplies have been connected separately
+IN OUTPUT A
such that V
V
CCI ≠ VCCO, care should be taken to bypass each of
–IN
these supplies separately to the GND plane. A bypass between them is futile and defeats the purpose of having separate pins. It is recommended that the GND plane separate the VCCI and VCCO
A2 Q2
planes when the circuit board layout is designed to minimize 2 coupling between the two supplies and to take advantage of the -01
GAIN STAGE OUTPUT STAGE
15 additional bypass capacitance from each respective supply to 59 0 Figure 14. Simplified Schematic Diagram of the ground plane. This enhances the performance when split TTL-/CMOS-Compatible Output Stage input/output supplies are used. If the input and output supplies are connected together for single-supply operation such that VCCI =
USING/DISABLING THE LATCH FEATURE
VCCO, coupling between the two supplies is unavoidable; however, The latch input is designed for maximum versatility. It can careful board placement can help keep output return currents safely be left floating for fixed hysteresis or be tied to V away from the inputs. CC to remove the hysteresis, or it can be driven low by any standard
TTL-/CMOS-COMPATIBLE OUTPUT STAGE
TTL/CMOS device as a high speed latch. Specified propagation delay performance can be achieved only In addition, the pin can be operated as a hysteresis control pin by keeping the capacitive load at or below the specified minimums. with a bias voltage of 1.25 V nominal and an input resistance of The low skew complementary outputs of the ADCMP603 are approximately 7000 Ω, allowing the comparator hysteresis to be designed to directly drive one Schottky TTL or three low power easily controlled by either a resistor or an inexpensive CMOS DAC. Schottky TTL loads or the equivalent. For large fan outputs, Hysteresis control and latch mode can be used together if an buses, or transmission lines, use an appropriate buffer to open drain, an open collector, or a three-state driver is connected maintain the excellent speed and stability of the comparator. parallel to the hysteresis control resistor or current source. With the rated 5 pF load capacitance applied, more than half of Due to the programmable hysteresis feature, the logic threshold the total device propagation delay is output stage slew time, of the latch pin is approximately 1.1 V regardless of VCC. even at 2.5 V VCC. Because of this, the total prop delay decreases as VCCO decreases, and instability in the power supply may appear as excess delay dispersion. Rev. A | Page 10 of 16 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ELECTRICAL CHARACTERISTICS TIMING INFORMATION ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS APPLICATIONS INFORMATION POWER/GROUND LAYOUT AND BYPASSING TTL-/CMOS-COMPATIBLE OUTPUT STAGE USING/DISABLING THE LATCH FEATURE OPTIMIZING PERFORMANCE COMPARATOR PROPAGATION DELAY DISPERSION COMPARATOR HYSTERESIS CROSSOVER BIAS POINT MINIMUM INPUT SLEW RATE REQUIREMENT TYPICAL APPLICATION CIRCUITS OUTLINE DIMENSIONS ORDERING GUIDE