Datasheet ADCMP380 (Analog Devices) - 8

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ADCMP380 Data Sheet THEORY OF OPERATION
The ADCMP380 ultralow power voltage comparator is especial y
UVLO VCC R
suited for battery-powered applications due to the maximum 190 nA quiescent current. The internal precision reference
tPD tPD
and the low input leakage current al ow the user to monitor the
V IN REF + VHYST VREF
voltage of interest accurately through external resistor dividers. The device features internal input hysteresis and an open-drain output. The output remains logic high after the voltage on the
OUT
IN pin is above the internal reference voltage. The device keeps the output in a logic low state whenever the supply voltage on the VCC pin is below the UVLO threshold. The output can be
EN EXTERNALLY EN DRIVEN LOW
disabled and remains low if the EN pin is pulled low, regardless of 014 the status of the IN pin.
tD_EN tD_EN
12783- Figure 14. Timing Diagram
TRANSIENT IMMUNITY ADDING HYSTERESIS
To avoid unnecessary output state change caused by fast power supply transients, an input glitch filter is added to the IN pin of To prevent oscillations at the output caused by noise or slowly the ADCMP380 to filter out the transient glitches on the pin. moving signals passing the switching threshold, positive feedback can add hysteresis to the input. Figure 8 shows the comparator overdrive (that is, the maximum magnitude of positive and negative going pulses with respect to For the configuration shown in Figure 15, connect the bottom the reference voltage) vs. the pulse duration without changing end of the input resistor divider to the output; the effective the state of the output. threshold is altered based on the output state.
OUTPUT
The input falling threshold level is given by V (R1+ R2 + R ) The output of ADCMP380 comparator is open-drain. The V R1 REF PULLUP SUPPLY V = – output is guaranteed to be logic low from when V IN _ FALL + CC = 0.9 V to R2 RPULLUP when the device exits ULVO. where VREF = 0.6 V, assuming RLOAD >> R2 and RPULLUP, where When the IN voltage fal s below the internal reference voltage, RLOAD is the resistance on the load. the OUT pin asserts low within 23 μs (typical). When the The input rising threshold level is given by monitored voltage rises above the reference voltage plus hysteresis, the OUT pin asserts high within 39.5 μs. V (R1+ R2) V REF = IN _ RISE R2
EN INPUT
The additional hysteresis is the difference between these voltage Driving EN low asserts the output low. The EN input has a levels and is given by 0.6 MΩ internal pull-up resistor so that the input is always high when unconnected. To drive the EN input, use an external signal V R1R +V R1R2 REF PULLUP SUPPLY V ∆ = or a push-button switch to ground; debounce circuitry is integrated IN R2 × R2 + R2 × RPULLUP on-chip for this purpose. Noise immunity is provided on the EN Note that the built in hysteresis of the device is neglected in this input, and fast, negative going transients of up to 0.4 μs (typical) are calculation. ignored. If required, a 0.1 μF capacitor between the EN pin and
V
ground provides additional noise immunity.
SUPPLY VCC RPULLUP ADCMP380 EN OUT V R1 IN IN R REF LOAD R2 GND
015 12783- Figure 15. Configuration with Added Hysteresis Rev. A | Page 8 of 10 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION TRANSIENT IMMUNITY OUTPUT EN INPUT ADDING HYSTERESIS DEVICE OPTIONS OUTLINE DIMENSIONS ORDERING GUIDE