Datasheet AK5706 (Asahi Kasei Microdevices) - 7

HerstellerAsahi Kasei Microdevices
BeschreibungLow-Power 2-ch ADC with AAA and Audio Buffer
Seiten / Seite33 / 7 — 5.4. Pin State in Power-down Mode
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DokumentenspracheEnglisch

5.4. Pin State in Power-down Mode

5.4 Pin State in Power-down Mode

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[AK5706]
5.4. Pin State in Power-down Mode
Register Power-down Pin Power-down No. Pin Name I/O (PDN pin = “H (PDN pin = “L” ,” ) all PMx bit = 0x0) F5 AVDD - - - Pull-down to VSS1 by 290 (Typ.) @ AVDD = 3.3 V F6 VCOM O see prev. column Pull-down to VSS1 by 300 (Typ.) @ AVDD = 1.8 V F4 VSS1 - - - E1 MPWR1 O Hi-z see prev. column F1 MPWR2 O Hi-z see prev. column E6 AAAIN I Hi-z see prev. column AIN1P I E2 Hi-z see prev. column DMDAT1 I AIN1N I E3 Hi-z see prev. column DMCLK1 O AIN2P I F2 Hi-z see prev. column DMDAT2 I AIN2N I F3 Hi-z see prev. column DMCLK2 O B1 WAKEUP O Hi-z see prev. column C1 EXTTRIG I Hi-z see prev. column C6 TVDD - - - B6 VDD12 - Internal pull-down to VSS2: 700 (Typ.) Normal Operation A6 VSS2 - - - MCKI I A5 Hi-z see prev. column XTI I A4 XTO O Internal pull-down to VSS2: 2 k (Typ.) see prev. column B5 BCLK I/O Internal pull-down to VSS2: 49 k (Typ.) Hi-z (MSN bit = “0”) C5 LRCK I/O Internal pull-down to VSS2: 49 k (Typ.) Hi-z (MSN bit = “0”) A3 SDTO O Internal pull-down to VSS2: 49 k (Typ.) “L” (VSS2) B3 TDMIN I Hi-z see prev. column FLAG O A1 Internal pull-down to VSS2: 49 k (Typ.) “L” (VSS2) MCKO O E4 SYNCTRIG I Hi-z see prev. column E5 I2CSEL I Hi-z see prev. column CSN I D1 Hi-z see prev. column CAD I SCLK I B4 Hi-z see prev. column SCL I SO O A2 Hi-z SO or SDA SDA I/O C2 SI I Hi-z Hi-z D2 SID I Hi-z Hi-z B2 DCSI I Hi-z Hi-z D6 PDN I Hi-z Hi-z D5 TEST I Hi-z Hi-z 200500012-E-00-PB 2020/05 - 7 - Document Outline 1. General Description 2. Features 3. Table of Contents 4. Block Diagram 5. Pin Configurations and Functions 5.1. Pin Configurations 5.2. Functions 5.3. Handling of Unused Pins 5.4. Pin State in Power-down Mode 6. Absolute Maximum Ratings 7. Recommended Operating Conditions 8. Electrical Characteristics 8.1. Microphone & ADC Analog Characteristics (AVDD = 3.3V: AVDDMD bit = “1”) 8.2. Microphone & ADC Analog Characteristics (AVDD = 1.8V: AVDDMD bit = “0”) 8.3. Acoustic Activity Analyzer Characteristics 8.4. PLL, AOSC Characteristics 8.5. LDO Characteristics 8.6. VCOM Characteristics 8.7. Power Supply Current 8.8. Power Consumption for Each Operation Mode (Typ.) 8.9. Filter Characteristics 8.9.1. Short Delay Sharp Roll-off Filter (ADVF bit = “0”) 8.9.2. Voice Filter (ADVF bit = “1”) 8.10. DC Characteristics 8.11. Switching Characteristics 9. Package 9.1. Outline Dimensions 9.2. Material & Lead finish 9.3. Marking 10. Ordering Guide 11. Revision History IMPORTANT NOTICE