Datasheet AD9363 (Analog Devices) - 7

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Data Sheet AD9363 Parameter1 Symbol Min Typ Max Unit Test Conditions/Comments
DIGITAL DATA TIMING (CMOS), VDD_INTERFACE = 2.5 V DATA_CLK_x Clock Period tCP 16.276 ns 61.44 MHz DATA_CLK_x and FB_CLK_x tMP 45% of tCP 55% of tCP ns Pulse Width Tx Data TX_FRAME_x, P0_Dx, and P1_Dx Setup to FB_CLK_x tSTX 1 ns Hold to FB_CLK_x tHTX 0 ns DATA_CLK_x to Data Bus tDDRX 0.25 1.25 ns Output Delay DATA_CLK_x to tDDDV 0.25 1.25 ns RX_FRAME_x Delay Pulse Width ENABLE tENPW tCP ns TXNRX tTXNRXPW tCP ns FDD independent ENSM mode TXNRX Setup to ENABLE tTXNRXSU 0 ns TDD ENSM mode Bus Turnaround Time TDD mode Before Rx tRPRE 2 × tCP ns After Rx tRPST 2 × tCP ns Capacitive Load 3 pF Capacitive Input 3 pF DIGITAL DATA TIMING (LVDS) DATA_CLK_x Clock Period tCP 4.069 ns 245.76 MHz DATA_CLK_x and FB_CLK_x tMP 45% of tCP 55% of tCP ns Pulse Width Tx Data TX_FRAME_x and TX_Dx Setup to FB_CLK_x tSTX 1 ns Hold to FB_CLK_x tHTX 0 ns DATA_CLK_x to Data Bus tDDRX 0 1.5 ns Output Delay DATA_CLK_x to tDDDV 0 1.0 ns RX_FRAME_x Delay Pulse Width ENABLE tENPW tCP ns TXNRX tTXNRXPW tCP ns FDD independent ENSM mode TXNRX Setup to ENABLE tTXNRXSU 0 ns TDD ENSM mode Bus Turnaround Time Before Rx tRPRE 2 × tCP ns After Rx tRPST 2 × tCP ns Capacitive Load 3 pF Capacitive Input 3 pF SUPPLY CHARACTERISTICS 1.3 V Main Supply 1.267 1.3 1.33 V VDD_INTERFACE Supply CMOS 1.2 2.5 V LVDS 1.8 2.5 V VDD_GPO Supply 1.3 3.3 3.465 V When unused, must be set to 1.3 V Current Consumption VDDx, Sleep Mode 180 µA Sum of all input currents VDD_GPO 50 μA No load 1 When referencing a single function of a multifunction pin in the parameters, only the portion of the pin name that is relevant to the specification is listed. For full pin names of multifunction pins, refer to the Pin Configuration and Function Descriptions section. Rev. D | Page 7 of 32 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS CURRENT CONSUMPTION—VDD_INTERFACE CURRENT CONSUMPTION—VDDx (COMBINATION OF ALL 1.3 V SUPPLIES) ABSOLUTE MAXIMUM RATINGS REFLOW PROFILE THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS 800 MHZ FREQUENCY BAND 2.4 GHZ FREQUENCY BAND THEORY OF OPERATION GENERAL RECEIVER TRANSMITTER CLOCK INPUT OPTIONS SYNTHESIZERS RF PLLs BB PLL DIGITAL DATA INTERFACE DATA_CLK Signal FB_CLK Signal RX_FRAME and TX_FRAME Signals ENABLE STATE MACHINE SPI Control Mode Pin Control Mode SPI INTERFACE CONTROL PINS Control Outputs (CTRL_OUT7 to CTRL_OUT0) Control Inputs (CTRL_IN3 to CTRL_IN0) GPO PINS (GPO_3 TO GPO_0) AUXILIARY CONVERTERS AUXADC AUXDAC1 and AUXDAC2 POWERING THE AD9363 APPLICATIONS INFORMATION PACKAGING AND ORDERING INFORMATION OUTLINE DIMENSIONS ORDERING GUIDE