Datasheet AD9363 (Analog Devices) - 6

AD9363 Data Sheet Parameter1 Symbol Min Typ Max Unit Test Conditions/Comments
Receiver Differential Input 100 Ω Impedance Logic Outputs Output Voltage High 1375 mV Output Voltage Low 1025 mV Output Differential 150 mV Programmable in 75 mV steps Voltage Output Offset Voltage 1200 mV GENERAL-PURPOSE OUTPUTS Output Voltage High VDD_GPO × 0.8 VDD_GPO V Output Voltage Low 0 VDD_GPO × 0.2 V Output Current 10 mA SPI TIMING VDD_INTERFACE = 1.8 V SPI_CLK Period tCP 20 ns Pulse Width tMP 9 ns SPI_EN Setup to First tSC 1 ns SPI_CLK Rising Edge Last SPI_CLK Falling Edge to tHC 0 ns SPI_ENB Hold SPI_DI Data Input Setup to tS 2 ns SPI_CLK Data Input Hold to tH 1 ns SPI_CLK SPI_CLK Rising Edge to Output Data Delay 4-Wire Mode tCO 3 8 ns 3-Wire Mode tCO 3 8 ns Bus Turnaround Time, Read tHZM tH tCO (MAX) ns After baseband processors (Master) (BBP) drives the last address bit Bus Turnaround Time, Read tHZS 0 tCO (MAX) ns After AD9363 drives the last (Slave) data bit DIGITAL DATA TIMING (CMOS), VDD_INTERFACE = 1.8 V DATA_CLK_x Clock Period tCP 16.276 ns 61.44 MHz DATA_CLK_x and FB_CLK_x tMP 45% of tCP 55% of tCP ns Pulse Width Tx Data TX_FRAME_x, P0_Dx, and P1_Dx Setup to FB_CLK_x tSTX 1 ns Hold to FB_CLK_x tHTX 0 ns DATA_CLK_x to Data Bus tDDRX 0 1.5 ns Output Delay DATA_CLK_x to tDDDV 0 1.0 ns RX_FRAME_x Delay Pulse Width ENABLE tENPW tCP ns TXNRX tTXNRXPW tCP ns FDD independent enable state machine (ENSM) mode TXNRX Setup to ENABLE tTXNRXSU 0 ns TDD ENSM mode Bus Turnaround Time TDD mode Before Rx tRPRE 2 × tCP ns After Rx tRPST 2 × tCP ns Capacitive Load 3 pF Capacitive Input 3 pF Rev. D | Page 6 of 32 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS CURRENT CONSUMPTION—VDD_INTERFACE CURRENT CONSUMPTION—VDDx (COMBINATION OF ALL 1.3 V SUPPLIES) ABSOLUTE MAXIMUM RATINGS REFLOW PROFILE THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS 800 MHZ FREQUENCY BAND 2.4 GHZ FREQUENCY BAND THEORY OF OPERATION GENERAL RECEIVER TRANSMITTER CLOCK INPUT OPTIONS SYNTHESIZERS RF PLLs BB PLL DIGITAL DATA INTERFACE DATA_CLK Signal FB_CLK Signal RX_FRAME and TX_FRAME Signals ENABLE STATE MACHINE SPI Control Mode Pin Control Mode SPI INTERFACE CONTROL PINS Control Outputs (CTRL_OUT7 to CTRL_OUT0) Control Inputs (CTRL_IN3 to CTRL_IN0) GPO PINS (GPO_3 TO GPO_0) AUXILIARY CONVERTERS AUXADC AUXDAC1 and AUXDAC2 POWERING THE AD9363 APPLICATIONS INFORMATION PACKAGING AND ORDERING INFORMATION OUTLINE DIMENSIONS ORDERING GUIDE