Datasheet LTC4362-1, LTC4362-2 (Analog Devices) - 8

link to page 8 LTC4362-1/LTC4362-2
APPLICATIONS INFORMATION
or ON above 1.5V (V
ON Input
ON(TH)) for more than 500µs. After reset, the LTC4362-1 goes through the start-up cycle. In ON is a CMOS compatible, active low enable input. It has applications not requiring the overcurrent protection, tie a default 5µA pull-down to ground. Connect this pin to SENSE and the exposed pad to the IN pin. ground or leave open to enable normal device operation. If it is driven high while the MOSFET is turned on, the
PWRGD Output
MOSFET is turned off gradual y with an internal 40µA PWRGD is an active low output with a MOSFET pull-down gate pull-down, minimizing input voltage transients. The to ground and a 500k resistive pull-up to OUT. The PWRGD LTC4362 then goes into a low current sleep mode, draw- pin pul -down releases during the low current sleep mode ing only 1.5µA at IN. When ON goes back low, the part (invoked by ON high), UVLO, overvoltage, overcurrent restarts with a 130ms delay cycle. or thermal shutdown and the subsequent 130ms start- up delay. After the start-up delay, the internal MOSFET
GATEP Control
gate starts its 3V/ms ramp-up and control of the PWRGD GATEP has a 2M resistive pull-down to ground and a 5.8V pull-down passes on to the internal gate high compara- Zener clamp in series with a 200k resistor to IN. It controls tor. When the internal gate is higher than the gate high the gate of an optional external P-channel MOSFET to pro- threshold for more than 65ms, PWRGD asserts low. When vide negative voltage protection. The 2M pull-down turns the internal gate goes lower than the gate high threshold, on the external P-channel MOSFET once VIN is more than the PWRGD pull-down releases. The PWRGD pull-down the P-channel MOSFET gate threshold voltage. The IN to device is capable of sinking up to 3mA of current allowing GATEP Zener protects the external P-channel MOSFET it to drive an optional LED. To interface PWRGD to another from gate overvoltage by clamping its VGS to 5.8V when I/O rail, connect a resistor from PWRGD to that I/O rail VIN goes high. with a resistance low enough to override the internal 500k pull-up to OUT. Figure 2 details PWRGD behavior for a LTC4362-2 with 1k pull-up to 5V at PWRGD. START-UP RESTART RESTART OC RESTART FROM UVLO OV FROM OV ON FROM ON FROM OC OC THRESHOLD ICABLE VIN(OV) VIN(OV) – ∆VOV VIN(UVL) IN OUT INTERNAL GATE HIGH GATE HIGH GATE HIGH GATE HIGH GATE HIGH MOSFET THRESHOLD THRESHOLD THRESHOLD THRESHOLD THRESHOLD GATE ON PWRGD 130ms 65ms 130ms 65ms 130ms 65ms 130ms 65ms 10µs (NOT TO SCALE) 436212 F02
Figure 2. PWRGD Behavior
Rev. B 8 For more information www.analog.com Document Outline Features Applications Typical Application Description Absolute Maximum Ratings order information Pin Configuration Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Package Description Revision History Typical Application Related Parts