Datasheet ADuCM4050 (Analog Devices) - 10

ADuCM4050 Data Sheet ADC SPECIFICATIONS Table 8. Parameter1, 2 Min Typ3 Max Unit Test Conditions/Comments
INTEGRAL NONLINEARITY ERROR 64-Lead LFCSP ±1.6 LSB 1.8 V (VBAT)/1.25 V (internal/external VREF) 4 64-Lead LFCSP −1.7 to +1.3 LSB 3.0 V (VBAT)/2.5 V (internal/external VREF)4 72-Ball WLCSP ±1.4 LSB 1.8 V (VBAT)/1.25 V (internal/external VREF)4 DIFFERENTIAL NONLINEARITY ERROR 64-Lead LFCSP −0.7 to +1.15 LSB 1.8 V (VBAT)/1.25 V (internal/external VREF)4 64-Lead LFCSP −0.7 to +1.1 LSB 3.0 V (VBAT)/2.5 V (internal/external VREF)4 72-Ball WLCSP −0.75 to +1.0 LSB 1.8 V (VBAT)/1.25 V (internal/external VREF)4 OFFSET ERROR 64-Lead LFCSP ±0.5 LSB 1.8 V (VBAT)/1.25 V (external VREF)4 64-Lead LFCSP ±0.5 LSB 3.0 V (VBAT)/2.5 V (external VREF)4 72-Ball WLCSP ±0.5 LSB 1.8 V (VBAT)/1.25 V (external VREF)4 GAIN ERROR 64-Lead LFCSP ±2.5 LSB 1.8 V (VBAT)/1.25 V (external VREF)4 64-Lead LFCSP ±0.5 LSB 3.0 V (VBAT)/2.5 V (external VREF)4 72-Ball WLCSP ±3.0 LSB 1.8 V (VBAT)/1.25 V (external VREF)4 I V 5 BAT_ADC 64-Lead LFCSP 129 µA 1.8 V (VBAT)/1.25 V (internal VREF)6 64-Lead LFCSP 157 µA 3.0 V (VBAT)/2.5 V (internal VREF)6 72-Ball WLCSP 124 µA 1.8 V (VBAT)/1.25 V (internal VREF) 6 64-Lead LFCSP 47 µA 1.8 V (VBAT)/1.25 V (external VREF)7 64-Lead LFCSP 51 µA 3.0 V (VBAT)/2.5 V (external VREF)7 72-Ball WLCSP 46 µA 1.8 V (VBAT)/1.25 V (external VREF) 7 INTERNAL REFERENCE VOLTAGE 1.25 V Internal reference, 1.25 V selected 2.50 V Internal reference, 2.5 V selected ADC SAMPLING FREQUENCY (fS)8 0.01 1.8 MSPS 1 The ADC is characterized in standalone mode without core activity and minimal or no switching on the adjacent ADC channels and digital inputs/outputs. 2 The specifications are characterized after performing internal ADC offset calibration. 3 TJ = 25°C. 4 fIN = 1068 Hz, fS = 100 kSPS, internal reference in low power mode, 400,000 samples end point method used. 5 Current consumption from VBAT_ADC supply when ADC is performing the conversion. 6 fIN = 1068 Hz, fS = 100 kSPS, internal reference in low power mode. 7 fIN = 1068 Hz, fS = 100 kSPS, sine wave with 1.25 V p-p applied at ADC0_VIN1 channel input. 8 Effects of analog source impedance must be considered when selecting ADC sampling frequency. Rev. A | Page 10 of 46 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM REVISION HISTORY GENERAL DESCRIPTION PRODUCT HIGHLIGHTS SPECIFICATIONS OPERATING CONDITIONS AND ELECTRICAL CHARACTERISTICS EMBEDDED FLASH SPECIFICATIONS POWER SUPPLY CURRENT SPECIFICATIONS Active Mode Flexi Mode Deep Sleep Modes—VBAT = 1.8 V Deep Sleep Modes—VBAT = 3.0 V Deep Sleep Modes—VBAT = 3.6 V ADC SPECIFICATIONS TEMPERATURE SENSOR SPECIFICATIONS SYSTEM CLOCKS External Crystal Oscillator Specifications On-Chip Resistor-Capacitor (RC) Oscillator Specifications System Clocks and Phase-Locked Loop (PLL) Specifications TIMING SPECIFICATIONS Reset Timing Serial Ports Timing SPI Timing I2C Specifications General-Purpose Port Timing RTC1 (FLEX_RTC) Specifications Timer Pulse-Width Modulation (PWM) Output Cycle Timing ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION ARM CORTEX-M4F PROCESSOR ARM Cortex-M4F Subsystem Code Region SRAM Region System Region MEMORY ARCHITECTURE SRAM Region MMRs (Peripheral Control and Status) Flash Memory Cache Controller SYSTEM INTEGRATION FEATURES Reset Booting Power Management and Modes Active Mode Flexi Mode Hibernate Mode Shutdown Mode Shutdown Mode—Fast Wake-Up Power Management and Control Security Features Cryptographic Accelerator True Random Number Generator (TRNG) Reliability and Robustness Features ECC Enabled Flash Memory Multiparity Bit Protected SRAM Software Watchdog CRC Accelerator Programmable GPIOs Timers General-Purpose Timers Watchdog Timer (WDT) RGB Timer ADC Subsystem Clocking Clock Fail Detection Real-Time Clock (RTC) Beeper Driver Debug Capability ON-CHIP PERIPHERAL FEATURES Serial Ports (SPORT) SPI Ports UART Ports I2C DEVELOPMENT SUPPORT Documentation Hardware Software REFERENCE DESIGNS SECURITY FEATURES DISCLAIMER MCU TEST CONDITIONS DRIVER TYPES EEMBC ULPMARK™-CP SCORE GPIO MULTIPLEXING APPLICATIONS INFORMATION SILICON ANOMALY ADuCM4050 FUNCTIONALITY ISSUES FUNCTIONALITY ISSUES SECTION 1. ADuCM4050 FUNCTIONALITY ISSUES OUTLINE DIMENSIONS ORDERING GUIDE