Datasheet AD5593R (Analog Devices) - 3

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Data Sheet AD5593R SPECIFICATIONS
VDD = 2.7 V to 5.5 V, VREF = 2.5 V (internal), TA = TMIN to TMAX, unless otherwise noted.
Table 2. Parameter Min Typ Max Unit Test Conditions/Comments
ADC PERFORMANCE fIN = 10 kHz sine wave Resolution 12 Bits Input Range1 0 VREF V ADC range select bit = 0 0 2 × VREF V ADC range select bit = 1 Integral Nonlinearity (INL) −2 +2 LSB Differential Nonlinearity (DNL) −1 +1 LSB Offset Error ±5 mV Gain Error 0.3 % FSR Track Time (tTRACK)2 500 ns Conversion Time (tCONV)2 2 µs Signal to Noise Ratio (SNR)3 69 dB VDD = 2.7 V, input range = 0 V to VREF 67 dB VDD = 5.5 V, input range = 0 V to VREF 61 dB VDD = 5.5 V, input range = 0 V to 2 × VREF Signal-to-Noise + Distortion (SINAD) 69 dB VDD = 2.7 V, input range = 0 V to VREF Ratio 67 dB VDD = 3.3 V, input range = 0 V to VREF 60 dB VDD = 5.5 V, input range = 0 V to 2 × VREF Total Harmonic Distortion (THD) −91 dB VDD = 2.7 V, input range = 0 V to VREF −89 dB VDD = 3.3 V, input range = 0 V to VREF −72 dB VDD = 5.5 V, input range = 0 V to 2 × VREF Spurious Free Dynamic Range (SFDR) 91 dB VDD = 2.7 V, input range = 0 V to VREF 91 dB VDD = 3.3 V, input range = 0 V to VREF 72 dB VDD = 5.5 V, input range = 0 V to 2 × VREF Aperture Delay2 15 ns VDD = 3 V 12 ns VDD = 5 V Aperture Jitter2 50 ps Channel-to-Channel Isolation −95 dB fIN = 5 kHz Full Power Bandwidth 8.2 MHz At 3 dB 1.6 MHz At 0.1 dB DAC PERFORMANCE4 Resolution 12 Bits Output Range 0 VREF V DAC range select bit = 0 0 2 × VREF V DAC range select bit = 1 INL −1 +1 LSB DNL −1 +1 LSB Offset Error −3 +3 mV Offset Error Drift2 8 µV/°C Gain Error ±0.2 % FSR Output range = 0 V to VREF ±0.1 % FSR Output range = 0 V to 2 × VREF Zero Code Error 0.65 2 mV Total Unadjusted Error (TUE) ±0.03 ±0.25 % FSR Output range = 0 V to VREF ±0.015 ±0.1 % FSR Output range = 0 V to 2 × VREF Capacitive Load Stability 2 nF RLOAD = ∞ 10 nF RLOAD = 1 kΩ Resistive Load 1 kΩ Short-Circuit Current 25 mA DC Crosstalk2 −4 +4 µV Single channel, full-scale output change DC Output Impedance 0.2 Ω DC Power Supply Rejection Ratio (PSRR)2 0.15 mV/V DAC code = midscale, VDD = 3 V ± 10% or 5 V ± 10% Load Impedance at Rails5 25 Ω Rev. D | Page 3 of 33 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Timing Characteristics Timing Diagram Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Terminology Theory of Operation DAC Section Resistor String DAC Output Buffer ADC Section Calculating ADC Input Current GPIO Section Internal Reference Reset Function Temperature Indicator Serial Interface Write Operation Read Operation Pointer Byte Control Registers General-Purpose Control Register Configuring the AD5593R DAC Write Operation LDAC Mode Operation DAC Readback ADC Operation GPIO Operation Setting Pins as Outputs Setting Pins as Inputs Three-State Pins 85 kΩ Pull-Down Pins Power-Down/Reference Control Reset Function Applications Information Microprocessor Interfacing AD5593R to ADSP-BF537 Interface Layout Guidelines Outline Dimensions Ordering Guide