Datasheet AD5593R (Analog Devices) - 5

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Data Sheet AD5593R Parameter Min Typ Max Unit Test Conditions/Comments
LOGIC INPUTS Input Voltage High, VINH 0.7 × VLOGIC V Low, VINL 0.3 × VLOGIC V Input Current, IIN −1 +0.01 +1 µA Input Capacitance, CIN 10 pF LOGIC OUTPUT (SDA) Output High Voltage, VOH VLOGIC − 0.2 V ISOURCE = 200 µA; VDD = 2.7 V to 5.5 V Output Low Voltage, VOL 0.4 V ISINK = 200 µA Floating-State Output Capacitance 10 pF TEMPERATURE SENSOR2 Resolution 12 Bits Operating Range −40 +105 °C Accuracy ±3 °C Track Time 5 µs ADC buffer enabled 20 µs ADC buffer disabled POWER REQUIREMENTS VDD 2.7 5.5 V IDD 2.7 Digital inputs = 0 V or VDD Power-Down Mode 3.5 µA Normal Mode VDD = 5 V 1.6 mA I/O0 to I/O7 are DACs, internal reference, gain = 2 1 mA I/O0 to I/O7 are DACs, external reference, gain = 2 2.4 mA I/O0 to I/O7 are DACs and sampled by the ADC, internal reference, gain = 2 1.1 mA I/O0 to I/O7 are DACs and sampled by the ADC, external reference, gain = 2 1 mA I/O0 to I/O7 are ADCs, internal reference, gain = 2 0.75 mA I/O0 to I/O7 are ADCs, external reference, gain = 2 0.5 mA I/O0 to I/O7 are general-purpose outputs 0.5 mA I/O0 to I/O7 are general-purpose inputs VDD = 3 V 1.1 mA I/O0 to I/O7 are DACs, internal reference, gain = 1 1 mA I/O0 to I/O7 are DACs, external reference, gain = 1 1.1 mA I/O0 to I/O7 are DACs and sampled by the ADC, internal reference, gain = 1 0.78 mA I/O0 to I/O7 are DACs and sampled by the ADC, external reference, gain = 1 0.75 mA I/O0 to I/O7 are ADCs, internal reference, gain = 1 0.5 mA I/O0 to I/O7 are ADCs, external reference, gain = 1 0.45 mA I/O0 to I/O7 are general-purpose outputs 0.45 mA I/O0 to I/O7 are general-purpose inputs VLOGIC 1.8 VDD V ILOGIC 3.5 μA 1 When using the internal ADC buffer, there is a dead band of 0 V to 5 mV. 2 Guaranteed by design and characterization; not production tested. 3 All specifications expressed in decibels are referred to full-scale input, FSR, and tested with an input signal at 0.5 dB below full scale, unless otherwise specified. 4 DC specifications tested with the outputs unloaded, unless otherwise noted. Linearity calculated using a reduced code range of 8 to 4085. An upper dead band of 10 mV exists when VREF = VDD. 5 When drawing a load current at either rail, the output voltage headroom with respect to that rail is limited by the 25 Ω typical channel resistance of the output devices. For example, when sinking 1 mA, the minimum output voltage = 25 Ω × 1 mA = 25 mV (see Figure 26 and Figure 27). Rev. D | Page 5 of 33 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Timing Characteristics Timing Diagram Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Terminology Theory of Operation DAC Section Resistor String DAC Output Buffer ADC Section Calculating ADC Input Current GPIO Section Internal Reference Reset Function Temperature Indicator Serial Interface Write Operation Read Operation Pointer Byte Control Registers General-Purpose Control Register Configuring the AD5593R DAC Write Operation LDAC Mode Operation DAC Readback ADC Operation GPIO Operation Setting Pins as Outputs Setting Pins as Inputs Three-State Pins 85 kΩ Pull-Down Pins Power-Down/Reference Control Reset Function Applications Information Microprocessor Interfacing AD5593R to ADSP-BF537 Interface Layout Guidelines Outline Dimensions Ordering Guide