Datasheet SZ8463ML, SZ8463RL, SZ8463FML, SZ8463FML (Microchip)

KSZ8463ML/RL/FML/FRL IEEE 1588 Precision Time Protocol-Enabled, Three-Port, 10/100 Managed Switch with MII or RMII Features
Port 2 and Source Address Filtering for Imple- menting Ring Topologies
Management Capabilities
• MAC Filtering Function to Filter or Forward • The KSZ8463ML/RL/FML/FRL Includes All the Unknown Unicast Packets Functions of a 10/100BASE-T/TX/FX Switch Sys- • Port 1 and Port 2 MACs Programmable as Either tem that Combines a Switch Engine, Frame Buffer E2E or P2P Transparent Clock (TC) Ports for Management, Address Look-Up Table, Queue 1588 Support Management, MIB Counters, Media Access Con- • Port 3 MAC Programmable as Slave or Master of trollers (MAC) and PHY Transceivers Ordinary Clock (OC) Port for 1588 Support • Non-Blocking Store-and-Forward Switch Fabric • Microchip LinkMD® Cable Diagnostic Capabilities Ensures Fast Packet Delivery by Utilizing 1024 for Determining Cable Opens, Shorts, and Length Entry Forwarding Table • Port Mirroring/Monitoring/Sniffing: Ingress and/or
Advanced Switch Capabilities
Egress Traffic to any Port • Non-Blocking Store-and-Forward Switch Fabric • MIB Counters for Fully Compliant Statistics Gath- Ensures Fast Packet Delivery by Utilizing 1024 ering: 34 Counters per Port Entry Forwarding Table • Loopback Modes for Remote Failure Diagnostics • IEEE 802.1Q VLAN for Up to 16 Groups with Full • Rapid Spanning Tree Protocol Support (RSTP) for Range of VLAN IDs Topology Management and Ring/Linear Recovery • IEEE 802.1p/Q Tag Insertion or Removal on a per • Bypass Mode Ensures Continuity Even When a Port Basis (Egress) and Support Double-Tagging Host is Disabled or Fails • VLAN ID Tag/Untag Options on per Port Basis • Fully Compliant with IEEE 802.3/802.3u Stan-
Robust PHY Ports
dards • Two Integrated IEEE 802.3/802.3u-Compliant • IEEE 802.3x Full-Duplex with Force-Mode Option Ethernet Transceivers Supporting 10BASE-T and and Half-Duplex Backpressure Collision Flow 100BASE-TX Control • Copper and 100BASE-FX Fiber Mode Support in • IEEE 802.1w Rapid Spanning Tree Protocol Sup- the KSZ8463FML and KSZ8463FRL port • Copper Mode Support in the KSZ8463ML and • IGMP v1/v2/v3 Snooping for Multicast Packet Fil- KSZ8463RL tering • On-Chip Termination Resistors and Internal Bias- • QoS/CoS Packets Prioritization Support: 802.1p, ing for Differential Pairs to Reduce Power DiffServ-Based and Re-Mapping of 802.1p Prior- • HP Auto MDI/MDI-X Crossover Support Elimi- ity Field per Port Basis on Four Priority Levels nates the Need to Differentiate Between Straight • IPv4/IPv6 QoS Support or Crossover Cables in Applications • IPv6 Multicast Listener Discovery (MLD) Snoop-
MAC Ports
ing Support • Three Internal Media Access Control (MAC) Units • Programmable Rate Limiting at the Ingress and • MII or RMII Interface Support on MAC Port 3 Egress Ports • 2Kbyte Jumbo Packet Support • Broadcast Storm Protection • Tail Tagging Mode (One byte Added before FCS) • Bypass Mode to Sustain the Switch Function Support at Port 3 to Inform The Processor Which between Port 1 and Port 2 when CPU (Port 3) Ingress Port Receives the Packet and its Priority Goes into Sleep Mode • Supports Reduced Media Independent Interface • 1K Entry Forwarding Table with 32K Frame Buffer (RMII) with 50 MHz Reference Clock Input or Out- • Four Priority Queues with Dynamic Packet Map- put ping for IEEE 802.1p, IPv4 TOS (DIFFSERV), • Supports Media Independent Interface (MII) in IPv6 Traffic Class, etc. Either PHY Mode or MAC Mode on Port 3 • Programmable MAC Addresses for Port 1 and  2018 Microchip Technology Inc. DS00002642A-page 1 Document Outline 1.0 Introduction 1.1 General Terms and Conditions 1.2 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Physical (PHY) Block 3.2 Media Access Controller (MAC) Block 3.3 Switch Block 3.4 IEEE 1588 Precision Time Protocol (PTP) Block 3.5 General Purpose and IEEE 1588 Input/Output (GPIO) 3.6 Using the GPIO Pins with the Trigger Output Units 3.7 Using the GPIO Pins with the Time Stamp Input Units 3.8 Device Clocks 3.9 Power 3.10 Power Management 3.11 Interrupt Generation on Power Management-Related Events 3.12 Interfaces 4.0 Register Descriptions 4.1 Register Map of CPU Accessible I/O Registers 4.2 Register Bit Definitions 4.3 MII Management (MIIM) Registers 4.4 Management Information Base (MIB) Counters 4.5 Static MAC Address Table 4.6 Dynamic MAC Address Table 4.7 VLAN Table 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Specifications 7.1 MII Transmit Timing in MAC Mode 7.2 MII Receive Timing in MAC Mode 7.3 MII Receive Timing in PHY Mode 7.4 MII Transmit Timing in PHY Mode 7.5 Reduced MII (RMII) Timing 7.6 MIIM (MDC/MDIO) Timing 7.7 SPI Input and Output Timing 7.8 Auto-Negotiation Timing 7.9 Trigger Output Unit and Time Stamp Input Unit Timing 7.10 Reset and Power Sequence Timing 7.11 Reset Circuit 8.0 Reference Clock: Connection and Selection 9.0 Selection of Isolation Transformers 10.0 Package Outline Appendix A: Data Sheet Revision History The Microchip Web Site Customer Change Notification Service Customer Support Product Identification System Worldwide Sales and Service