Datasheet SZ8463ML, SZ8463RL, SZ8463FML, SZ8463FML (Microchip) - 5

KSZ8463ML/RL/FML/FRL 1.0 INTRODUCTION 1.1 General Terms and Conditions
The following is list of the general terms used throughout this document:
BIU - Bus Interface Unit
The host interface function that performs code conversion, buffering, and the like required for communications to and from a network.
BPDU - Bridge Protocol Data Unit
A packet containing ports, addresses, etc. to make sure data being passed through a bridged network arrives at its proper destination.
CMOS - Complementary Metal Oxide
A common semiconductor manufacturing technique in which positive
Semiconductor
and negative types of transistors are combined to form a current gate that in turn forms an effective means of controlling electrical current through a chip.
CRC - Cyclic Redundancy Check
A common technique for detecting data transmission errors. CRC for Ethernet is 32 bits long.
Cut-Through Switch
A switch typically processes received packets by reading in the full packet (storing), then processing the packet to determine where it needs to go, then forwarding it. A cut-through switch simply reads in the first bit of an incoming packet and forwards the packet. Cut- through switches do not store the packet.
DA - Destination Address
The address to send packets.
EMI - Electro-Magnetic Interference
A naturally occurring phenomena when the electromagnetic field of one device disrupts, impedes or degrades the electromagnetic field of another device by coming into proximity with it. In computer tech- nology, computer devices are susceptible to EMI because electro- magnetic fields are a byproduct of passing electricity through a wire. Data lines that have not been properly shielded are susceptible to data corruption by EMI.
FCS - Frame Check Sequence
See CRC.
FID - Frame or Filter ID
Specifies the frame identifier. Alternately is the filter identifier.
GPIO - General Purpose Input/Output
General Purpose Input/Output pins are signal pins that can be con- trolled or monitored by hardware and software to perform specific tasks.
IGMP - Internet Group Management
The protocol defined by RFC 1112 for IP multicast transmissions.
Protocol IPG - Inter-Packet Gap
A time delay between successive data packets mandated by the net- work standard for protocol reasons. In Ethernet, the medium has to be "silent" (i.e., no data transfer) for a short period of time before a node can consider the network idle and start to transmit. IPG is used to correct timing differences between a transmitter and receiver. During the IPG, no data is transferred, and information in the gap can be discarded or additions inserted without impact on data integrity.
ISA - Industry Standard Architecture
A bus architecture used in the IBM PC/XT and PC/AT.
ISI - Inter-Symbol Interference
The disruption of transmitted code caused by adjacent pulses affect- ing or interfering with each other.
Jumbo Packet
A packet larger than the standard Ethernet packet (1500 bytes). Large packet sizes allow for more efficient use of bandwidth, lower overhead, less processing, etc.
MAC - Media Access Controller
A functional block responsible for implementing the media access control layer which is a sub layer of the data link layer.
MDI - Medium Dependent Interface
An Ethernet port connection that allows network hubs or switches to connect to other hubs or switches without a null-modem, or cross- over, cable. MDI provides the standard interface to a particular media (copper or fiber) and is therefore “media dependent”.  2018 Microchip Technology Inc. DS00002642A-page 5 Document Outline 1.0 Introduction 1.1 General Terms and Conditions 1.2 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Physical (PHY) Block 3.2 Media Access Controller (MAC) Block 3.3 Switch Block 3.4 IEEE 1588 Precision Time Protocol (PTP) Block 3.5 General Purpose and IEEE 1588 Input/Output (GPIO) 3.6 Using the GPIO Pins with the Trigger Output Units 3.7 Using the GPIO Pins with the Time Stamp Input Units 3.8 Device Clocks 3.9 Power 3.10 Power Management 3.11 Interrupt Generation on Power Management-Related Events 3.12 Interfaces 4.0 Register Descriptions 4.1 Register Map of CPU Accessible I/O Registers 4.2 Register Bit Definitions 4.3 MII Management (MIIM) Registers 4.4 Management Information Base (MIB) Counters 4.5 Static MAC Address Table 4.6 Dynamic MAC Address Table 4.7 VLAN Table 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Specifications 7.1 MII Transmit Timing in MAC Mode 7.2 MII Receive Timing in MAC Mode 7.3 MII Receive Timing in PHY Mode 7.4 MII Transmit Timing in PHY Mode 7.5 Reduced MII (RMII) Timing 7.6 MIIM (MDC/MDIO) Timing 7.7 SPI Input and Output Timing 7.8 Auto-Negotiation Timing 7.9 Trigger Output Unit and Time Stamp Input Unit Timing 7.10 Reset and Power Sequence Timing 7.11 Reset Circuit 8.0 Reference Clock: Connection and Selection 9.0 Selection of Isolation Transformers 10.0 Package Outline Appendix A: Data Sheet Revision History The Microchip Web Site Customer Change Notification Service Customer Support Product Identification System Worldwide Sales and Service