Datasheet TPD7107F (Toshiba) - 7
Hersteller | Toshiba |
Beschreibung | Intelligent Power Device Silicon Power MOS Integrated Circuit |
Seiten / Seite | 34 / 7 — TPD7107F. 7.4. Load current sense at time of Power MOSFET drive. Figure … |
Dateiformat / Größe | PDF / 1.1 Mb |
Dokumentensprache | Englisch |
TPD7107F. 7.4. Load current sense at time of Power MOSFET drive. Figure 7.7 Current sense amp circuit
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TPD7107F 7.4. Load current sense at time of Power MOSFET drive
For A/D-converter detection via the DIAG pin, the current sense amplifier and the pul up for diagnosis circuit in Figure7.7 carry out the conversion from the current which flows into the shunt resistance Rs to the voltage.
Figure 7.7 Current sense amp circuit.
Load current sense output voltage is calculated as below. In addition, when abnormalities are detected, a load current sense output mode is changes to a diagnostic output mode. And the fixed voltage according to the diagnosis results is outputted. 𝑅𝑅2 𝑉𝑉𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷 = 𝑅𝑅1 × (𝑅𝑅𝑆𝑆 × 𝐼𝐼𝑂𝑂 + 𝑉𝑉𝐷𝐷𝑂𝑂) ● VDIAG: DIAG pin output voltage ● IO: load current ● VIO: Input offset voltage
7.5. The abnormalities in power supply voltage (VDD over voltage, VDD under voltage)
● When the voltage of a VDD terminal is more than the over voltage detection threshold (VOV), the off- driver usual y operates and the external FET turns of . After that, if the VDD terminal voltage is less than the over voltage threshold voltage, the external FET is driven again. ‒ In the case of VIN=H and VDD>VOV, the off-driver operates after the mask time of TOV (200us max) (VGATE=H to L). ‒ In the case of VDD>VOV and VIN=L to H, it keeps VGATE=L. ● When VDD terminal voltage is less than VUV3 (2.7V (typ.)), the rapid off-driver operates, carry out latch- off of the external FET, and outputs H state to DIAG. ● In case VDD<VUV5, the off-driver operates and VDD goes up. After that, if VDD is more than VUV5, the off- driver wil change to normal operation. ● Even if VDD terminal voltage fal s under the conditions of VGATE=H, VGATE keeps H state, and external FET will be ON in VDD>VUV3.(Low-voltage extension operation) © 2 020 7 2020-04-09 Toshiba Electronic Devices & Storage Corporation Document Outline 1. Description 2. Uses 3. Features 4. Block Diagram 5. Pin Assignments 6. Pin Description 7. Operational Description 7.1. Protection for reverse connection of power supply 7.2. Active clamp 7.3. Gate drive of Power MOSFET (Off driver) 7.3.1. Normal off, rapid off 7.3.2. Protection for disconnection of GND terminal 7.4. Load current sense at time of Power MOSFET drive 7.5. The abnormalities in power supply voltage (VDD over voltage, VDD under voltage) 7.6. Over current protection 7.7. Over temperature protection. 7.8. Abnormalities in voltage between Drain and source of the external FET (VDS error) 7.9. Load open / VDD short of load line and diagnosis output 7.10. Truth Table 7.11. State Transition Diagram 8. Absolute Maximum Ratings 8.1. Thermal Resistance 9. Operating Ranges 10. Electrical Characteristics 10.1. Electrical characteristics 1 10.2. Electrical characteristics 2 10.3. Current sense amp Electrical Characteristics 11. Test Circuit 11.1. Test circuit 1 High level output voltage (3) 11.2. Test circuit 2 Switching time (Td-ON, Td-OFF, Tr, Tf) 11.3. Test circuit 3 Off impedance at GND open 11.4. Test circuit 4 Input offset voltage 12. Characteristic curves 13. Package Information 13.1. Package Dimensions 13.2. Marking 13.3. Land Pattern Dimensions for Reference only 14. IC Usage Notes 14.1. Notes on Handling of ICs 14.2. Notes on mounting. RESTRICTIONS ON PRODUCT USE