Datasheet ADN8810 (Analog Devices) - 10

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ADN8810 Data Sheet FUNCTIONAL DESCRIPTION
The ADN8810 is a single 12-bit current output digital-to-analog • DVDD provides power for the digital circuitry. This converter (DAC) with a 3-wire SPI interface. Up to eight devices includes the serial interface logic, the SB and RESET logic can be independently programmed from the same SPI bus. inputs, and the FAULT output. Tie DVDD to the same The ful -scale output current is set with two external resistors. supply line used for other digital circuitry. It is not The maximum output current can reach 300 mA. Figure 17 necessary for DVDD to be low noise. shows the functional block diagram of the ADN8810. • PVDD is the power pin for the output amplifier. It can
DVDD AVDD FAULT FB ENCOMP
operate from as low as 3.0 V to minimize power dissipation in the ADN8810. For best performance, PVDD must be
BIAS FAULT SB
low noise.
GEN DETECTION 1.5kΩ PVDD
Current is returned through the following three pins:
VREF PVDD 12-BIT
• AVSS is the return path for both AVDD and PVDD. This
DAC IOUT
pin is connected to the substrate of the die as wel as the
IOUT
slug on the bottom of the lead frame chip scale package
CS AVSS 12-BIT
(LFCSP). For single-supply operation, connect this pin to a
DATA LATCH 1.5kΩ SCLK CONTROL
low noise ground plane.
LOGIC RSN SDI ADDRESS 15kΩ DECODER
• DVSS returns current from the digital circuitry powered by 017 0- DVDD. Connect DVSS to the same ground line or plane
DGND ADDR2 ADDR1 ADDR0 RESET DVSS
03195- used for other digital devices in the application. Figure 17. Functional Blocks, Pins, and Internal Connections • DGND is the ground reference for the digital circuitry. In a
SETTING FULL-SCALE OUTPUT CURRENT
single-supply application, connect DGND to DVSS. Two external resistors set the full-scale output current from the For single-supply operation, set AVDD to 5 V, set PVDD from ADN8810. These resistors are equal in value and are labeled RSN 3.0 V to 5 V, and connect AVSS, AGND, and DGND to ground. in Figure 1. Use 1% or better tolerance resistors to achieve the
SERIAL DATA INTERFACE
most accurate output current and the highest output impedance. The ADN8810 uses a serial peripheral interface (SPI) with three input signals: SDI, CLK, and CS. Figure 2 shows the timing Equation 3 shows the approximate ful -scale output current. diagram for these signals. The exact output current is determined by the data register code as shown in Equation 4. The variable code is an integer from 0 Data applied to the SDI pin is clocked into the input shift to 4095, representing the ful 12-bit range of the ADN8810. register on the rising edge of CLK. After al 16 bits of the data- word have been clocked into the input shift register, a logic high I ≈ 4.096 on CS loads the shift register byte into the ADN8810. If more FS (3) 10× SN R than 16 bits of data are clocked into the shift register before CS   goes high, bits are pushed out of the register in first-in first-out = Code I × 1 ×  RSN +  (4) OUT  0.1 (FIFO) fashion. 000 ,1 RSN 15 Ω k  The four MSB of the data byte are checked against the address The ADN8810 is designed to operate with a 4.096 V reference of the device. If they match, the next 12 bits of the data byte are voltage connected to VREF. The output current is directly loaded into the DAC to set the output current. The first bit proportional to this reference voltage. To achieve the best (MSB) of the data byte must be a logic zero, and the following performance, use a low noise precision (the ADR292, ADR392, three bits must correspond to the logic levels on pins ADDR2, or REF198 is recommended). ADDR1, and ADDR0, respectively, for the DAC to be updated.
POWER SUPPLIES
Up to eight ADN8810 devices with unique addresses can be driven from the same serial data bus. There are three principal supply current paths through the ADN8810: Table 5 shows how the 16-bit DATA input word is divided into an address byte and a data byte. The first four bits in the input • AVDD provides power to the analog front end of the word correspond to the address. Note that the first bit loaded ADN8810 including the DAC. Use this supply line to (A3) must always be zero. The remaining bits set the 12-bit data power the external voltage reference. For best performance, byte for the DAC output. Three example inputs are demonstrated. AVDD must be low noise. Rev. C | Page 10 of 14 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY FUNCTIONAL DESCRIPTION SETTING FULL-SCALE OUTPUT CURRENT POWER SUPPLIES SERIAL DATA INTERFACE STANDBY AND RESET MODES POWER DISSIPATION USING MULTIPLE ADN8810 DEVICES FOR ADDITIONAL OUTPUT CURRENT ADDING DITHER TO THE OUTPUT CURRENT DRIVING COMMON-ANODE LASER DIODES PCB LAYOUT RECOMMENDATIONS SUGGESTED PAD LAYOUT FOR CP-24 PACKAGE OUTLINE DIMENSIONS ORDERING GUIDE