Datasheet ADN8810 (Analog Devices) - 4

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ADN8810 Data Sheet Parameter Symbol Test Conditions/Comments Min Typ Max Unit
LOGIC INPUTS Input Leakage Current IIL 1 µA Input Low Voltage VIL DVDD = 3.0 V 0.5 V DVDD = 5 V 0.8 V Input High Voltage VIH DVDD = 3.0 V 2.4 V DVDD = 5 V 4 V INTERFACE TIMING3 Clock Frequency fCLK 12.5 MHz RESET Pulse Width t11 40 ns 1 With respect to AVSS. 2 RSN = 20 Ω. 3 See Table 2 for timing specifications.
TIMING CHARACTERISTICS Table 2. Timing Characteristics1, 2 Parameter Description Min Typ Max Unit
fCLK SCLK frequency 12.5 MHz t1 SCLK cycle time 80 ns t2 SCLK width high 40 ns t3 SCLK width low 40 ns t4 CS low to SCLK high setup 15 ns t5 CS high to SCLK high setup 15 ns t6 SCLK high to CS low hold 35 ns t7 SCLK high to CS high hold 20 ns t8 Data setup 15 ns t9 Data hold 2 ns t10 CS high pulse width 30 ns t11 RESET pulse width 40 ns t12 CS high to RESET low hold 30 ns 1 Guaranteed by design. Not production tested. 2 Sample tested during initial release and after any redesign or process change that may affect these parameters. All input signals are measured with tr = tf = 5 ns (10% to 90% of DVDD) and timed from a voltage level of (VIL + VIH)/2.
t1 SCLK t6 t t t 3 t2 5 4 t7 C S t10 t8 t9 SDI A3* A2 A1 A0 D11 D10 D0 t12 t11 RESET *ADDRESS BIT A3 MUST BE LOGIC LOW
03195-0-002 Figure 2. Timing Diagram Rev. C | Page 4 of 14 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY FUNCTIONAL DESCRIPTION SETTING FULL-SCALE OUTPUT CURRENT POWER SUPPLIES SERIAL DATA INTERFACE STANDBY AND RESET MODES POWER DISSIPATION USING MULTIPLE ADN8810 DEVICES FOR ADDITIONAL OUTPUT CURRENT ADDING DITHER TO THE OUTPUT CURRENT DRIVING COMMON-ANODE LASER DIODES PCB LAYOUT RECOMMENDATIONS SUGGESTED PAD LAYOUT FOR CP-24 PACKAGE OUTLINE DIMENSIONS ORDERING GUIDE