Datasheet STUSB4500L (STMicroelectronics) - 7

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STUSB4500L Pin description 2.2.9 GPIO
This pin is an active low open drain output that can be configured by NVM as per table below (see Section 5 Start-up configuration).
Table 5. GPIO pin configuration NVM parameter Pin name Pin function Value Description GPIO_CFG[1:0]
Software controlled GPIO. Hi-Z When bit #0 value is 0b (at start-up) 00b SW_CTRL_GPIO The output state is defined by the value of I2C register bit #0 0 When bit #0 value is 1b at address 2Dh Hardware fault detection Hi-Z No hardware fault detected 01b ERROR_RECOVERY (see Section 3.5 Hardware fault management) 0 Hardware fault detected Debug accessory detection Hi-Z No debug accessory detected 10b DEBUG (see Section 3.6 Debug accessory mode detection) 0 Debug accessory detected Source supplies default or 1.5 A USB Hi-Z 11b Indicates USB Type-C current Type-C current at 5 V SINK_POWER capability advertised by the (default) source Source supplies 3.0 A USB Type-C 0 current at 5 V
2.2.10 VBUS_EN_SNK
This pin allows the incoming VBUS power from the USB Type-C receptacle to be enabled when a source is connected according to different operating conditions stated in the table below. VBUS_EN_SNK pin is a high voltage open drain output that allows a PMOS transistor to be directly driven to enable the VBUS power path.
2.2.11 A_B_SIDE
This output pin provides the cable orientation. It is used to establish USB SuperSpeed signal routing. This signal is not required in case of USB 2.0 support.
Table 6. USB data MUX select Value Description
HiZ CC1 pin is attached to CC line 0 CC2 pin is attached to CC line
2.2.12 VBUS_VS_DISCH
This input pin is used to sense VBUS presence, monitor VBUS voltage, and discharge VBUS from the USB Type-C receptacle side. A serial resistor connected to the pin must be used to limit the discharge current through the pin. Maximum discharge current is 50 mA. The discharge is activated automatically during cable disconnection, and error recovery state. The discharge time is programmable by NVM (see Section 5 Start-up configuration).
2.2.13 VREG_1V2
This pin is used only for external decoupling of the 1.2 V internal regulator. The recommended decoupling capacitor is: 1 µF typ. (0.5 µF min., 10 µF max.)
2.2.14 VSYS
This is the low power supply from the system, if there is any. It can be connected directly to a single cell Lithium battery or to the system power supply delivering 3.3 V up to 5 V. It is recommended to connect the pin to ground when it is not used.
DS13102
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Document Outline Cover image Product status link / summary Product status link / summary Features Applications Description 1 Functional description 1.1 Block overview 2 Inputs/outputs 2.1 Pinout 2.2 Pin description 2.2.1 CC1 / CC2 2.2.2 CC1DB / CC2DB 2.2.3 RESET 2.2.4 I²C interface pins 2.2.5 DISCH 2.2.6 GND 2.2.7 ATTACH 2.2.8 RP_3A/RP_1A5 2.2.9 GPIO 2.2.10 VBUS_EN_SNK 2.2.11 A_B_SIDE 2.2.12 VBUS_VS_DISCH 2.2.13 VREG_1V2 2.2.14 VSYS 2.2.15 VREG_2V7 2.2.16 VDD 3 Description of the features 3.1 CC interface 3.2 VBUS power path control 3.2.1 VBUS monitoring 3.2.2 VBUS discharge 3.2.3 VBUS power path assertion 3.3 Dead battery mode 3.4 High voltage protections 3.5 Hardware fault management 3.6 Debug accessory mode detection 4 I²C Interface 4.1 Read and write operations 4.2 Timing specifications 5 Start-up configuration 5.1 User-defined parameters 5.2 Default start-up configuration 6 Application 6.1 General information 6.1.1 Power supplies 6.1.2 Connection to MCU or application processor 6.2 Typical application 7 Electrical characteristics 7.1 Absolute maximum ratings 7.2 Operating conditions 7.3 Electrical and timing characteristics 8 Package information 8.1 QFN-24 EP (4x4) package information 8.2 WLCSP (2.6x2.6x0.5) 25 bumps package information 8.3 Thermal information 9 Terms and abbreviations Revision history