Preliminary Datasheet EZ-PD CCG6DF, CCG6SF (Cypress) - 5

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PRELIMINARY EZ-PD CCG6DF, CCG6SF Functional Overview
The RD resistors on CC pins are required even when the part is not powered on. This is required for dead battery termination
MCU Subsystem
detection and charging. To support the latest USB-PD 3.0 specification, CCG6DF and CPU CCG6SF devices implement the FRS feature. Fast Role Swap The Cortex M0 in CCG6DF and CCG6SF devices is a 32-bit enables externally powered docks and hubs to rapidly switch to MCU, which is optimized for low-power operation with extensive bus power when their external power supply is removed. This clock gating. It mostly uses 16-bit instructions and executes a feature is supported for provider N-FET Gate Driver Output subset of the Thumb-2 instruction set, which enables fully (NGDO). SCP and RCP fault detection are not enabled during compatible binary upward migration of code to higher perfor- the FRS sequence and it is assumed that provider side supply is mance processors such as Cortex M3 and M4. Also included is present and higher than 4.85 V. a hardware multiplier, which provides a 32-bit result in one cycle. It includes an Interrupt Controller (the NVIC block) with 32 CCG6DF and CCG6SF devices are designed to be fully interop- Interrupt inputs and a Wakeup Interrupt Controller (WIC), which erable with revision 3.0 of the USB Power Delivery specification can wake the processor up from Deep Sleep mode. as well as revision 2.0 of the USB Power Delivery specification. Flash, SROM, and RAM VCONN FET The 64-KB Flash and 96-KB ROM store the firmware CCG6DF and CCG6SF devices have power supply input V5V implementing PD functionality. pin for providing power to EMCA cables through integrated VCONN FETs. There are two VCONN FETs per port in CCG6DF The 16-KB RAM is used under software control to store and CCG6SF devices to power either CC1 or CC2 pins. These temporary status of system variables and parameters. A FETs source a minimum of 1.5-W power per port over the valid supervisory ROM that contains boot and configuration routines VCONN range of 4.85 V to 5.5 V on the CC1/2 pins when is provided. providing power to EMCA cables. At any given time, only one of the VCONN FETs is in ON state to provide VCONN on either
USB-PD Subsystem (SS)
CC1 or CC2 lines depending on the cable orientation. The This subsystem provides the interface to the Type-C USB port. floating V5V pin does not cause CCG6DF to malfunction and This subsystem comprises of: draw more current. ■ USB-PD Physical Layer ADC ■ VCONN FETs CCG6DF and CCG6SF devices have a low power 8-bit SAR ADC that has access to the chip-wide analog mux. All GPIOs on ■ ADC these devices have access to the ADCs through the chip-wide analog mux. ■ SBU pass-through switch and USB HS mux ■ Undervoltage, overvoltage and Reverse-Current Protection on SBU Pass-Through Switch and USB HS Mux VBUS CCG6DF has integrated 2x SBU pass-through switches and 2x high-speed (480 Mbps) switches as shown in Figure 1. ■ High-side current sense amplifier for VBUS The SBU switch is a simple pass-through switch. The Type-C ■ VBUS Discharge facing SBU pins are protected from accidental short to VBUS. ■ VBUS Regulator The HS mux contains a 2x2 cross bar switch to route the system DP/DM lines to the Type-C top or bottom lines as per the CC ■ Consumer Gate Driver for VBUS NFET (Type-C plug) orientation and connect the Debug pins to unused ■ Integrated VBUS Provider path load switch with FRS DP or DM top or bottom pins. ■ VBUS tolerant SBU and CC pins USB-PD Physical Layer The USB-PD subsystem contains the USB-PD physical layer block and supporting circuits. The USB-PD Physical Layer consists of a transmitter and receiver that communicate BMC encoded data over the CC channel per the PD 3.0 standard. All communication is half-duplex.The Physical Layer or PHY practices collision avoidance to minimize communication errors on the channel. In addition, the USB-PD block includes all termination resistors (RP and RD) and their switches as required by the USB Type-C spec. Rp and Rd resistors are required to implement connection detection, plug orientation detection and for establishment of the USB source/sink roles. The RP resistor is implemented as a current source. Document Number: 002-27161 Rev. *E Page 5 of 50 Document Outline EZ-PD CCG6DF, CCG6SF, USB Type-C Port Controller General Description Applications Features USB-PD Type-C Mux Integrated Provider VBUS Load Switch LDO 32-bit MCU Subsystem Integrated Digital Blocks Authentication Clocks and Oscillators Operating Range Hot-Swappable I/Os Packages Logic Block Diagram CCG6DF/CCG6SF Functional Diagram Contents Functional Overview MCU Subsystem CPU Flash, SROM, and RAM USB-PD Subsystem (SS) USB-PD Physical Layer VCONN FET ADC SBU Pass-Through Switch and USB HS Mux Provider Load Switch Undervoltage and Overvoltage Protection on VBUS High-side Current Sense Amplifier for VBUS VBUS Reverse Current Protection VBUS Short Circuit Protection VBUS Discharge VBUS Regulator Gate Driver for VBUS NFET VBUS Tolerant SBU and CC Lines Serial Communication Block (SCB) Timer, Counter, Pulse-Width Modulator (TCPWM) True Random Number Generator (TRNG) GPIO Interface System Resources Watchdog Timer (WDT) Clock System IMO Clock Source ILO Clock Source Power Pinouts Application Diagrams CCG6DF, CCG6SF Layout Design Guidelines for BGA Package Usage of Via Size of 8-mil drill/16-mil diameter and 10-mil drill/16-mil diameter Layer Stack-up Top Layer Fan Out Via Count for GND Pads Via Count for Provider Pads High-Speed (DP_SYS, DM_SYS) USB Connections CC Connections CC lines for CCG6DF/CCG6SF devices carry ~500-mA current. In the top layer, two CC pads are shorted using 0.2mm trace width and connected to other layers through one via. The capacitors are placed on bottom layer and are routed to the Type-C Connecto... Rsense and Capacitor Connections for Provider VBUS The differential signal from Rsense should be length matched. The capacitor for Provider VBUS should be as close as possible to the Rsense and connected using copper shape. Figure 19 and Figure 20 show routing for Rsense. Trace Width Details for Critical Signals VDDIO, VCCD, VSYS, and VDDD Connections Figure 21 and Figure 22 show how the VDDIO, VDDD, VSYS, and VCCD signals get routed amongst the top and bottom layers. Capacitor Connections for CC Lines and Bypass Capacitors for VDDIO, VDDD, VCCD, and VSYS Pins Figure 23 shows how the relevant capacitors can be placed for via sizes of 8-mil drill, 16-mil diameter or 10-mil drill, 16-mil diameter. Electrical Specifications Absolute Maximum Ratings Device-Level Specifications DC Specifications CPU GPIO XRES Digital Peripherals Pulse Width Modulation (PWM) for GPIO Pins I2C UART SPI Memory System Resources Power-on-Reset (POR) with Brown Out SWD Interface Internal Main Oscillator Internal Low-speed Oscillator PD Analog-to-Digital Converter VSYS Switch CSA VBUS UV/OV Provider Side RCP SBU Switch DP/DM Switch VCONN Switch VBUS Ordering Information Ordering Code Definitions Packaging Acronyms Document Conventions Units of Measure References and Links to Applications Collateral Knowledge Base Articles Application Notes Reference Designs Kits Datasheets Document History Page Sales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC® Solutions Cypress Developer Community Technical Support