Preliminary Datasheet EZ-PD CCG6DF, CCG6SF (Cypress) - 10

PRELIMINARY EZ-PD CCG6DF, CCG6SF Pinouts Table 2. Pinout for CYPD6227-96BZXI Group Name Pin Name Port Pin Description
CC1_P0 Analog B3 USB PD Port-0 connector detect/Configuration Channel 1 CC2_P0 Analog B5 USB PD Port-0 connector detect/Configuration Channel 2 USB Type-C CC1_P1 Analog K5 USB PD Port-1 connector detect/Configuration Channel 1 CC2_P1 Analog K3 USB PD Port-1 connector detect/Configuration Channel 2 DP_SYS_P0 Analog K11 USB 2.0 DP from the Host System: Port-0 DM_SYS_P0 Analog J11 USB 2.0 DM from the Host System: Port-0 UART_TX_P0/P1.4 GPIO H10 UART Tx from Host System: Port-0/GPIO UART_RX_P0/P1.3 GPIO G10 UART Rx from Host System: Port-0/GPIO DP_BOT_P0 Analog K10 USB 2.0 DP from Bottom of Type-C Connector: Port-0 DM_BOT_P0 Analog J10 USB 2.0 DM from Bottom of Type-C Connector: Port-0 DM_TOP_P0 Analog H11 USB 2.0 DM from Top of Type-C Connector: Port-0 DP_TOP_P0 Analog G11 USB 2.0 DP from Top of Type-C Connector: Port-0 SBU2_P0 Analog A4 Type-C Sideband Use signal – Connector side: Port-0 SBU1_P0 Analog A5 Type-C Sideband Use signal – Connector side: Port-0 SBU1_SYS_P0 Analog B6 Type-C Sideband Use signal – System side: Port-0 SBU2_SYS_P0 Analog A6 Type-C Sideband Use signal – System side: Port-0 Muxes/Switches DP_SYS_P1 Analog L6 USB 2.0 DP from the Host System: Port-1 DM_SYS_P1 Analog L5 USB 2.0 DM from the Host System: Port-1 UART_TX_P1/P0.0 GPIO L4 UART Tx from Host System: Port-1/GPIO UART_RX_P1/P0.1 GPIO K6 UART Rx from Host System: Port-1/GPIO DP_BOT_P1 Analog K8 USB 2.0 DP from Bottom of Type-C Connector: Port-1 DM_BOT_P1 Analog K7 USB 2.0 DM from Bottom of Type-C Connector Port-1 DM_TOP_P1 Analog L7 USB 2.0 DM from Top of Type-C Connector: Port-1 DP_TOP_P1 Analog L8 USB 2.0 DP from Top of Type-C Connector: Port-1 SBU2_P1 Analog A9 Type-C Sideband Use signal – Connector side: Port-1 SBU1_P1 Analog A8 Type-C Sideband Use signal – Connector side Port-1 SBU1_SYS_P1 Analog B7 Type-C Sideband Use signal – System side: Port-1 SBU2_SYS_P1 Analog A7 Type-C Sideband Use signal – System side: Port-1 VBUS_C_CTRL_P0 Analog A3 Full rail control I/O for enabling/disabling Consumer load NFET of USB Type-C Port-0 VBUS Control VBUS_C_CTRL_P1 Analog L3 Full rail control I/O for enabling/disabling Consumer load NFET of USB Type-C Port-1 CSP_P0 Analog A11 Current Sense Positive Input for VBUS side external Rsense: Port-0 CSN_P0 Analog A10 Current Sense Negative input for other side of external Rsense: Port-0 VBUS OCP CSP_P1 Analog L11 Current Sense Positive Input for VBUS side external Rsense: Port-1 CSN_P1 Analog L10 Current Sense Negative input for other side of external Rsense: Port-1 Document Number: 002-27161 Rev. *E Page 10 of 50 Document Outline EZ-PD CCG6DF, CCG6SF, USB Type-C Port Controller General Description Applications Features USB-PD Type-C Mux Integrated Provider VBUS Load Switch LDO 32-bit MCU Subsystem Integrated Digital Blocks Authentication Clocks and Oscillators Operating Range Hot-Swappable I/Os Packages Logic Block Diagram CCG6DF/CCG6SF Functional Diagram Contents Functional Overview MCU Subsystem CPU Flash, SROM, and RAM USB-PD Subsystem (SS) USB-PD Physical Layer VCONN FET ADC SBU Pass-Through Switch and USB HS Mux Provider Load Switch Undervoltage and Overvoltage Protection on VBUS High-side Current Sense Amplifier for VBUS VBUS Reverse Current Protection VBUS Short Circuit Protection VBUS Discharge VBUS Regulator Gate Driver for VBUS NFET VBUS Tolerant SBU and CC Lines Serial Communication Block (SCB) Timer, Counter, Pulse-Width Modulator (TCPWM) True Random Number Generator (TRNG) GPIO Interface System Resources Watchdog Timer (WDT) Clock System IMO Clock Source ILO Clock Source Power Pinouts Application Diagrams CCG6DF, CCG6SF Layout Design Guidelines for BGA Package Usage of Via Size of 8-mil drill/16-mil diameter and 10-mil drill/16-mil diameter Layer Stack-up Top Layer Fan Out Via Count for GND Pads Via Count for Provider Pads High-Speed (DP_SYS, DM_SYS) USB Connections CC Connections CC lines for CCG6DF/CCG6SF devices carry ~500-mA current. In the top layer, two CC pads are shorted using 0.2mm trace width and connected to other layers through one via. The capacitors are placed on bottom layer and are routed to the Type-C Connecto... Rsense and Capacitor Connections for Provider VBUS The differential signal from Rsense should be length matched. The capacitor for Provider VBUS should be as close as possible to the Rsense and connected using copper shape. Figure 19 and Figure 20 show routing for Rsense. Trace Width Details for Critical Signals VDDIO, VCCD, VSYS, and VDDD Connections Figure 21 and Figure 22 show how the VDDIO, VDDD, VSYS, and VCCD signals get routed amongst the top and bottom layers. Capacitor Connections for CC Lines and Bypass Capacitors for VDDIO, VDDD, VCCD, and VSYS Pins Figure 23 shows how the relevant capacitors can be placed for via sizes of 8-mil drill, 16-mil diameter or 10-mil drill, 16-mil diameter. Electrical Specifications Absolute Maximum Ratings Device-Level Specifications DC Specifications CPU GPIO XRES Digital Peripherals Pulse Width Modulation (PWM) for GPIO Pins I2C UART SPI Memory System Resources Power-on-Reset (POR) with Brown Out SWD Interface Internal Main Oscillator Internal Low-speed Oscillator PD Analog-to-Digital Converter VSYS Switch CSA VBUS UV/OV Provider Side RCP SBU Switch DP/DM Switch VCONN Switch VBUS Ordering Information Ordering Code Definitions Packaging Acronyms Document Conventions Units of Measure References and Links to Applications Collateral Knowledge Base Articles Application Notes Reference Designs Kits Datasheets Document History Page Sales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC® Solutions Cypress Developer Community Technical Support