Datasheet AD74111 (Analog Devices) - 4

AD74111 (AVDD = 2.5 V
±
5%, DVDD2 = 2.5 V
±
5%, DVDD1 = 3.3 V
±
10%, f TIMING CHARACTERISTICS MCLK = 12.288 MHz, fS = 48 kHz, TA = TMIN to TMAX, unless otherwise noted.) Parameter Min Max Unit Comments
MASTER CLOCK AND RESET tMH MCLK High 25 ns tML MCLK Low 25 ns tRES RESET Low 10 ns tRS DIN Setup Time 5 MCLKS To RESET Rising Edge1 tRH DIN Setup Time 5 MCLKS To RESET Rising Edge1 SERIAL PORT tCH DCLK High2 20 ns tCL DCLK Low2 20 ns tFD DFS Delay 5 ns From DCLK Rising Edge3 tFS DFS Setup Time 5 ns To DCLK Falling Edge tFH DFS Hold Time 15 ns From DCLK Falling Edge tDD DOUT Delay 30 ns From DCLK Rising Edge tDS DIN Setup Time 5 ns To DCLK Falling Edge tDH DIN Hold Time 15 ns From DCLK Falling Edge tDT DOUT Three-State 40 ns From DCLK Rising Edge4 NOTES 1Determines Master/Slave mode operation. 2Applies in Slave mode only. 3Applies in Master mode only. 4Applies in Multiframe-Sync mode only.
tMH MCLK tML RESET tRES DIN tRS tRH
Figure 1. MCLK and RESET Timing
tFS DFS tFH tCH DCLK t t FD CL MSB MSB–1 DIN MSB–2 tDS tDH DOUT MSB MSB–1 MSB–2 tDD
Figure 2. Serial Port Timing
100 A IOL TO OUTPUT DVDD1 PIN C 2 L 50pF 100 A IOH
Figure 3. Load Circuit for Digital Output Timing Specifications –4– REV. 0 Document Outline FEATURES FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION SPECIFICATIONS TIMING CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS TEMPERATURE RANGE ORDERING GUIDE PIN CONFIGURATION PIN FUNCTION DESCRIPTIONS Typical Performance Characteristics FUNCTIONAL DESCRIPTION General Description ADC Section ADC, CAPP, and CAPN Pins Peak Readback Decimator Section Input Signal Swing DAC Section Output Signal Swing Low Group Delay Reference Master Clocking Scheme Selecting Sample Rates Resetting the AD74111 Power Supplies and Grounds Accessing the Internal Registers Serial Port Serial Port Operating Modes Mixed Mode Data Mode Data-Word Length Selecting Master or Slave Mode Master Mode Operation Slave Mode Operation OUTLINE DIMENSIONS