Datasheet AD74111 (Analog Devices) - 10

AD74111 Example 2: fSAMP = 44.1 kHz and 11.025 kHz Required
MCLK = 44.1 kHz ⫻ 256 = 11.2896 MHz to provide 44.1 kHz fSAMP.
1.125V REFCAP
For f
EXTERNAL
SAMP = 11.025 kHz, it is necessary to use the ⫼1 setting in
REFERENCE
Prescaler 1 and the ⫼4 setting in Prescaler 2, and pass through in Prescaler 3. This results in an IMCLK = 11.025 kHz ⫻ 256 = 2.8224 MHz (= 11.2896 MHz/4). Figure 9. External Reference
Resetting the AD74111 Master Clocking Scheme
The AD74111 can be reset by bringing the RESET pin low. The update rate of the AD74111’s ADC and DAC channels Following a reset, the internal circuitry of the AD74111 ensures requires an internal master clock (IMCLK) that is 256 times the that the internal registers are reset to their default settings and sample update rate (IMCLK = 256 ⫻ fS). To provide some flex- the on-chip RAM is purged of previous data samples. The DIN ibility in selecting sample rates, the device has a series of three pin is sampled to determine if the AD74111 is required to master clock prescalers that are programmable and allow the operate in Master or Slave mode. The reset process takes 3072 user to choose a range of convenient sample rates from a single MCLK periods, and the user should not attempt to program the external master clock. The master clock signal to the AD74111 is AD74111 during this time. applied at the MCLK pin. The MCLK signal is passed through a series of three programmable MCLK prescaler (divider) circuits
Power Supplies and Grounds
that can be selected to reduce the resulting Internal MCLK The AD74111 features three separate supplies: AVDD, DVDD1, (IMCLK) frequency if required. The first and second MCLK and DVDD2. prescalers provide divider ratios of ⫼1 (pass through), ⫼2, ⫼3; AVDD is the supply to the analog section of the device and must while the third prescaler provides divider ratios of ⫼1 (pass be of sufficient quality to preserve the AD74111’s performance through), ⫼2, ⫼4. characteristics. It is nominally a 2.5 V supply.
PROGRAMMABLE MCLK DIVIDER
DVDD1 is the supply for the digital interface section of the device.
PRESCALER 1 PRESCALER 2 PRESCALER 3
It is fed from the digital supply voltage of the DSP or controller
/1 /1
to which the device is interfaced and allows the AD74111
MCLK /1 IMCLK /2 /2 /2
to interface with devices operating at supplies of between
/3 /3 /4
2.5 V – 5% to 3.3 V + 10%. DVDD2 is the supply for the digital core of the AD74111. It is nominally a 2.5 V supply.
CONTROL REGISTER Accessing the Internal Registers
Figure 10. MCLK Divider The AD74111 has seven registers that can be programmed to control the functions of the AD74111. Each register is 10 bits The divider ratios allow a more convenient sample rate selection wide and is written to or read from using a 16-bit write or read from a common MCLK, which may be required in many voice operation, with the exception of Control Register F, which is related applications. Control Register B should be programmed read-only. Table V shows the format of the data transfer operation. to achieve the desired divider ratios. The Control Word is made up of a Read/Write bit, the register
Selecting Sample Rates
address, and the data to be written to the device. Note that in a The sample rate at which the converter runs is always 256 times read operation the data field is ignored by the device. Access to the IMCLK rate. IMCLK is the Internal Master Clock and is the the control registers is via the serial port through one of the output from the Master Clock Prescaler. The default sample rate operating modes described below. is 48 kHz (based on an external MCLK of 12.288 MHz). In this
Serial Port
mode, the ADC modulator is clocked at 3.072 MHz and the DAC The AD74111 contains a flexible serial interface port that is modulator is clocked at 6.144 MHz. Sample rates that are lower used to program and read the control registers and to send and than MCLK/256 can be achieved by using the MCLK prescaler. receive DAC and ADC audio data. The serial port is compatible
Example 1: fSAMP = 48 kHz and 8 kHz Required
with many popular DSPs and can be programmed to operate in MCLK = 48 kHz ⫻ 256 = 12.288 MHz to provide 48 kHz fSAMP. a variety of modes, depending on which one best suits the DSP For f being used. The serial port can be set to operate as a Master or SAMP = 8 kHz, it is necessary to use the ⫼3 setting in Prescaler 1, the ⫼2 setting in Prescaler 2, and pass through Slave device, as discussed below. Figure 11 shows a timing in Prescaler 3. This results in an IMCLK = 8 kHz ⫻ 256 = diagram of the serial port. 2.048 MHz (= 12.288 MHz/6). –10– REV. 0 Document Outline FEATURES FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION SPECIFICATIONS TIMING CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS TEMPERATURE RANGE ORDERING GUIDE PIN CONFIGURATION PIN FUNCTION DESCRIPTIONS Typical Performance Characteristics FUNCTIONAL DESCRIPTION General Description ADC Section ADC, CAPP, and CAPN Pins Peak Readback Decimator Section Input Signal Swing DAC Section Output Signal Swing Low Group Delay Reference Master Clocking Scheme Selecting Sample Rates Resetting the AD74111 Power Supplies and Grounds Accessing the Internal Registers Serial Port Serial Port Operating Modes Mixed Mode Data Mode Data-Word Length Selecting Master or Slave Mode Master Mode Operation Slave Mode Operation OUTLINE DIMENSIONS