Datasheet XDPS21071 (Infineon) - 4

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Forced Frequency Resonant Flyback controller Pin Configuration and Functionality 1 Pin Configuration and Functionality
The pin configuration is shown in Figure 2 and the functions are described in Table 1. 1 12 ZCD GND 2 11 MFIO X VCC DP 3 10 GPIO GD0 S 4 CS 9 GD1 210 71 HV 5 8 HV HV 6 7 HV PG-DSO-12-20
Figure 2 Pin Configuration of XDPS21071 Table 1 Pin Definitions and Functions Symbol Pin Type Function
ZCD 1 I
Zero Crossing Detection
ZCD pin is connected to an auxiliary winding for zero crossing detection and positive pin voltage measurement. MFIO 2 I
Multi-Functional Input Output
MFIO pin is connected to an optocoupler that provides an amplified error signal for the PWM mode operation. GPIO 3 IO
Digital General Purpose Input Output
GPIO pin provides an UART interface until brown-in. It is switched to weak pull down mode and disabled UART function during normal operation. CS 4 I
Current Sense
CS pin is connected via a resistor in series to an external shunt resistor and the source of the power MOSFET. HV 5, 6, 7, 8 I
High Voltage Input
HV pin is connected to the rectified bulk voltage. An internally connected 600 V HV startup-cell is used for initial VCC charge. Furthermore brown-in and brownout detection is provided. GD1 9 I
FFR Signal Gate Driver Output
GD1 pin provides a gate driver pulse signal to initiate the forced frequency resonant mode operation. GD0 10 O
Gate Driver Output
Output for directly driving the main power MOSFET. VCC 11 I
Positive Voltage Supply
IC power supply. GND 12 O
Power and Signal Ground
Data Sheet 4 Revision 2.0 2019-10-30