Datasheet MTD1N60E (Motorola) - 5
| Hersteller | Motorola |
| Beschreibung | TMOS E−FET Power Field Effect Transistor DPAK for Surface Mount. N−Channel Enhancement−Mode Silicon Gate |
| Seiten / Seite | 10 / 5 — Figure 8. Gate−To−Source and Drain−To−Source. Figure 9. Resistive … |
| Revision | XXX |
| Dateiformat / Größe | PDF / 239 Kb |
| Dokumentensprache | Englisch |
Figure 8. Gate−To−Source and Drain−To−Source. Figure 9. Resistive Switching Time. Voltage versus Total Charge
Modelllinie für dieses Datenblatt
Textversion des Dokuments
MTD1N60E 12 600 V 100 TS) DS QT VDD = 300 V , DRAIN−T I 10 500 D = 1 A VGS = 10 V TAGE (VOL VGS TJ = 25°C 8 400 O−SOURCE VOL tf Q1 Q2 (ns) td(off) 6 300 10 td(on) ID = 1 A t, TIME O−SOURCE VOL TJ = 25°C tr 4 200 TAGE (VOL TE−T , GA 2 100 V GS Q3 V TS) DS 0 0 1 0 1 2 3 4 5 6 7 8 1 10 100 QT, TOTAL CHARGE (nC) RG, GATE RESISTANCE (OHMS)
Figure 8. Gate−To−Source and Drain−To−Source Figure 9. Resistive Switching Time Voltage versus Total Charge Variation versus Gate Resistance DRAIN−TO−SOURCE DIODE CHARACTERISTICS
1 VGS = 0 V TJ = 25°C 0.8 (AMPS) 0.6 0.4 , SOURCE CURRENT 0.2 I S 00.5 0.54 0.58 0.62 0.66 0.7 0.74 0.78 0.82 VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define able operation, the stored energy from circuit inductance dis- the maximum simultaneous drain−to−source voltage and sipated in the transistor while in avalanche must be less than drain current that a transistor can handle safely when it is for- the rated limit and adjusted for operating conditions differing ward biased. Curves are based upon maximum peak junc- from those specified. Although industry practice is to rate in tion temperature and a case temperature (TC) of 25°C. Peak terms of energy, avalanche energy capability is not a con- repetitive pulsed power limits are determined by using the stant. The energy rating decreases non−linearly with an in- thermal response data in conjunction with the procedures crease of peak current in avalanche and peak junction discussed in AN569, “Transient Thermal Resistance−General temperature. Data and Its Use.” Although many E−FETs can withstand the stress of drain− Switching between the off−state and the on−state may tra- to−source avalanche at currents up to rated pulsed current verse any load line provided neither rated peak current (IDM) nor rated voltage (V (IDM), the energy rating is specified at rated continuous cur- DSS) is exceeded and the transition time (t rent (I r,tf) do not exceed 10 µs. In addition the total power aver- D), in accordance with industry custom. The energy rat- aged over a complete switching cycle must not exceed ing must be derated for temperature as shown in the (T accompanying graph (Figure 12). Maximum energy at cur- J(MAX) − TC)/(RθJC). A Power MOSFET designated E−FET can be safely used rents below rated continuous ID can safely be assumed to in switching circuits with unclamped inductive loads. For reli- equal the values indicated. Motorola TMOS Power MOSFET Transistor Device Data 5
Figure 8. Gate−To−Source and Drain−To−Source Figure 9. Resistive Switching Time Voltage versus Total Charge Variation versus Gate Resistance DRAIN−TO−SOURCE DIODE CHARACTERISTICS
1 VGS = 0 V TJ = 25°C 0.8 (AMPS) 0.6 0.4 , SOURCE CURRENT 0.2 I S 00.5 0.54 0.58 0.62 0.66 0.7 0.74 0.78 0.82 VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define able operation, the stored energy from circuit inductance dis- the maximum simultaneous drain−to−source voltage and sipated in the transistor while in avalanche must be less than drain current that a transistor can handle safely when it is for- the rated limit and adjusted for operating conditions differing ward biased. Curves are based upon maximum peak junc- from those specified. Although industry practice is to rate in tion temperature and a case temperature (TC) of 25°C. Peak terms of energy, avalanche energy capability is not a con- repetitive pulsed power limits are determined by using the stant. The energy rating decreases non−linearly with an in- thermal response data in conjunction with the procedures crease of peak current in avalanche and peak junction discussed in AN569, “Transient Thermal Resistance−General temperature. Data and Its Use.” Although many E−FETs can withstand the stress of drain− Switching between the off−state and the on−state may tra- to−source avalanche at currents up to rated pulsed current verse any load line provided neither rated peak current (IDM) nor rated voltage (V (IDM), the energy rating is specified at rated continuous cur- DSS) is exceeded and the transition time (t rent (I r,tf) do not exceed 10 µs. In addition the total power aver- D), in accordance with industry custom. The energy rat- aged over a complete switching cycle must not exceed ing must be derated for temperature as shown in the (T accompanying graph (Figure 12). Maximum energy at cur- J(MAX) − TC)/(RθJC). A Power MOSFET designated E−FET can be safely used rents below rated continuous ID can safely be assumed to in switching circuits with unclamped inductive loads. For reli- equal the values indicated. Motorola TMOS Power MOSFET Transistor Device Data 5