Datasheet AD7741 (Analog Devices) - 10

AD7741 APPLICATIONS
The basic connection diagram for the part is shown in Figure 9.
f AD7741 OUT VIN COUNTER TO
␮
P
In the connection diagram shown, the AD7742 analog inputs are configured as fully differential, bipolar inputs with a gain of
GATE
1. A quartz crystal provides the master clock source for the part.
SIGNAL CLKIN FREQUENCY
It may be necessary to connect capacitors (C1 and C2 in the
DIVIDER
diagram) on the crystal to ensure that it does not oscillate at over-
CLOCK
tones of its fundamental operating frequency. The values of ca-
GENERATOR
pacitors will vary depending on the manufacturer’s specifications. Figure 10. A/D Conversion Using the AD7741 VFC
+5V 4096x TCLOCK fCLKIN V V DD PD IN1 DIFF REFOUT INPUT 1 VIN2 fOUT REFIN VIN3 AD7742 DIFF fOUT INPUT 2 VIN4 GATE TGATE GND A0 UNI/BIP CHANNEL
Figure 11. Waveforms in an A/D Converter Using a VFC
SELECT A1 GAIN
The clock frequency and the gate time determine the resolution of such an ADC. If 12-bit resolution is required and f
CLKIN CLKOUT
CLKIN is 5 MHz (therefore, fOUT max is 2.25 MHz), the minimum gate
C1 C2
time required is calculated as follows: N counts at Full Scale (2.25 MHz) will take Figure 9. Basic Connection Diagram (N/2.25 × 106) seconds = minimum gate time.
A/D Conversion Techniques Using the AD7741/AD7742
N is the total number of codes for a given resolution; 4096 for When used as an ADC, VFCs provide certain advantages in- 12 bits cluding accuracy, linearity and being inherently monotonic. The AD7741/AD7742 has a true integrating input which smooths minimum gate time = (4096/2.25 × 106) sec = 1.820 ms. out noise peaks. Since TGATE × fOUT max = number of counts at full scale, a The most popular method of using a VFC in an A/D system is faster conversion with the same resolution can be performed to count the output pulses of f with a higher fOUT max. This high fOUT max (3 MHz) is a main OUT for a fixed gate interval (see Figure 10). This fixed gate interval should be generated by feature of the AD7741/AD7742. dividing down the clock input frequency. This ensures that any If the output frequency is measured by counting pulses gated to errors due to clock jitter or clock frequency drift are eliminated. a signal which is derived from the clock, the clock stability is The ratio of the fOUT to the clock frequency is what is important unimportant and the device simply performs as a voltage- here, not the absolute value of fOUT. The frequency division can controlled frequency divider, producing a high resolution ADC. be done by a binary counter where fCLKIN is the CLK input. The inherent monotonicity of the transfer function and wide Figure 11 shows the waveforms of f range of input clock frequencies allows the conversion time and CLKIN, fOUT and the Gate signal. A counter counts the rising edges of f resolution to be optimized for specific applications. OUT while the Gate signal is high. Since the gate interval is not synchronized with There is another parameter is taken into account when choosing fOUT, there is a possibility of a counting inaccuracy. Depending the length of the gate interval. Because the integration period of on fOUT, an error of one count may occur. the system is equal to the gate interval, any interfering signal can be rejected by counting for an integer number of periods of the interfering signal. For example, a gate interval of 100 ms will give normal-mode rejection of 50 Hz and 60 Hz signals. –10– REV. A