Datasheet 5X2503 (IDT) - 10
Hersteller | IDT |
Beschreibung | MicroClock Programmable Clock Generator with Embedded Crystal |
Seiten / Seite | 30 / 10 — Electrical Characteristics–Input Parameters. Table 13. Electrical … |
Revision | 20171218 |
Dateiformat / Größe | PDF / 418 Kb |
Dokumentensprache | Englisch |
Electrical Characteristics–Input Parameters. Table 13. Electrical Characteristics–Input Parameters 1. Symbol. Parameter
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5X2503 Datasheet
Electrical Characteristics–Input Parameters
Supply Voltage VDD1_8 = 1.8V ±5%, VDDOUTx = 1.8V ±5%, TA = -40°C to +85°C.
Table 13. Electrical Characteristics–Input Parameters 1 Symbol Parameter Conditions Minimum Typical Maximum Units
IIL Input Leakage Low Current for OE1 VIN = GND at OE1 pin. 150 — 5 μA IIH Input Leakage High Current for OE1 VIN = 1.89V. — — 20 μA I_OE1 Input Leakage Current VIN = 1.89V at OE1 pin. — — 120 μA 1 Guaranteed by design and characterization; test in production.
DC Electrical Characteristics for 1.8V LVCMOS
VDD = 1.8V ±5%, VDDOUTx = 1.8V ±5%, TA = -40°C to 85°C.
Table 14. DC Electrical Characteristics – 1.8V LVCMOS Symbol Parameter Conditions Minimum Typical Maximum Units
VOH Output High Voltage IOH = -8mA. 0.7 × VDDOUTx — VDDOUTx V VOL Output Low Voltage IOL = 8mA. — — 0.25 × VDDOUTx V IOZDD Output Leakage Current Tri-state outputs, VDDOUTx = 1.89V. — — 3 μA VIH Input High Voltage Single-ended inputs – OE, SDA, SCL. 0.65 × VDDOUTx — VDDOUTx + 0.3 V VIL Input Low Voltage Single-ended inputs – OE, SDA, SCL. GND - 0.3 — 0.35 × VDDOUTx V
AC Electrical Characteristics Table 15. AC Timing Electrical Characteristics – 32.768kHz
VDD1_8 = 1.8V ±5%, VDDOUTx = 1.8V ±5%, TA = -40°C to +85°C; spread spectrum = off.
Symbol Parameter Conditions Minimum Typical Maximum Units
fOUT Initial Frequency Single-ended clock output limit (LVCMOS). 32.768 kHz f 1 OUT_ tor Frequency Tolerance At 25°C. -20 20 ppm t1 Output Duty Cycle Measured at 50%. 45 55 % 1 This measurement uses a 3-day average. ©2017 Integrated Device Technology, Inc 10 December 18, 2017 Document Outline Description Typical Applications Features Output Features Key Specifications Block Diagram Power Group Output Source Selection Register Setting Tables Pin Assignments Figure 1. Pin Assignments for 2.5 × 2.5 mm 12-DFN Package Pin Descriptions Table 1. Pin Descriptions Device Feature and Function DFC – Dynamic Frequency Control Figure 2. DFC Function Block Diagram Table 2. DFC Function Priority DFC Function Programming PPS – Proactive Power Saving Function Figure 3. PPS Function Block Diagram Figure 4. PPS Assertion/Deassertion Timing Chart PPS Function Programming Input Pin Function Table 3. OE1 Pin Function Table Table 4. SDA/SCL Function Selection Spread Spectrum ORT – VCO Overshoot Reduction Technology PLL Features and Descriptions Table 5. Output Divider 1 Table 6. Output Divider 2, 3, and 5 Table 7. Output Divider 4 Output Clock Test Conditions Figure 5. LVCMOS Output Clock Test Condition Absolute Maximum Ratings Table 8. Absolute Maximum Ratings Recommended Operating Conditions Table 9. Recommended Operating Conditions Input Capacitance, LVCMOS Output Impedance, and Internal Pull-down Resistance (TA = +25 °C) Table 10. Input Capacitance, LVCMOS Output Impedance, and Internal Pull-down Resistance Integrated Crystal Characteristics Table 11. Crystal Characteristics DC Electrical Characteristics Table 12. DC Electrical Characteristics 1,2 Electrical Characteristics–Input Parameters Table 13. Electrical Characteristics–Input Parameters 1 DC Electrical Characteristics for 1.8V LVCMOS Table 14. DC Electrical Characteristics – 1.8V LVCMOS AC Electrical Characteristics Table 15. AC Timing Electrical Characteristics – 32.768kHz Table 16. AC Timing Electrical Characteristics – 1.8V Table 17. AC Timing Electrical Characteristics, 1.2V / 1.8V I2C Bus DC Characteristics Table 18. I2C Bus DC Characteristics Table 19. I2C Bus AC Characteristics Spread Spectrum Generation Specifications Table 20. Spread Spectrum Generation Specifications General SMBus Serial Interface Information Package Outline Drawings Figure 6. NDG12 Package Drawing – page 1 Figure 7. NDG12 Package Drawing – page 2 Ordering Information Marking Diagram Revision History