Datasheet InnoSwitch3-CP (Power Integrations) - 9

InnoSwitch3-CP Applications Example
C1 1 nF 250 VAC R6 C6 C7 49.9 kΩ
5 V, 3 A
390 µF 390 µF Q1 1% Q2
9 V, 3 A
20 V 20 V BSC030P03NS3 G 1/10 W BSC030P03NS3 G
15 V, 3 A
FL1 FL3
VOUT
C5* C16 R7 6.8 nF 100 nF 200 Ω C4 R2 R4 50 V 50 V 1% BR1 BR2 2.2 nF 150 kΩ TBS20J-TP TBS20J-TP R8 C8 100 kΩ C17 630 V 1% FL4 600 V 600 V 10 Ω 1 nF 1% R10* 1 µF R1 R5 1% 200 V 4.02 kΩ C10 35 V 2.00 MΩ 20 Ω D1 1% 2.2 µF R9 C9 1% 1% DFLR1800-7 R23 1.00 kΩ 10 µF FL2 25 V 100 kΩ 1% 35 V 1% 1/8 W R25
CYPD2134
5 4.7 KΩ U2 Q R3 FL6
XRES VDDD
T1-GE3 R11 1.8 MΩ 3 10 Ω
GPIO10 VCCD
1% Q RJU003N03T106 1% 4
GPIO5 GPIO6
C11 330 pF Q FL5
I2C_SDA_P0.0 CC1
SIR882ADP- 50 V T1
I2C_SCL_P0.1 CC2
RJU003N03T106 EQ27 R24
GPIO7
C2 C3 CL R13 10 kΩ R12
EPAD
39 µF 1% 1 3 39 µF 47 Ω 100 kΩ 400 V 400 V R15 R14 1/10 W 6 1.5 MΩ T1G 402 Ω Q 1% L1 1% R16 34 mH 1% 7 2 4 Q 31.6 kΩ TA06L RU1J002YNT 1% R17 C20 C19 C18 C12 31.6 kΩ 330 pF 330 pF 1 µF 100 nF MMB C13 1% 16 V 16 V 16 V 305 VAC D2 -TP 2.2 µF 25 V V21WS-7-F R18* BA D3 18.0 kΩ 2 4 1% T1G SM4003PL R20
D V FWD SR VO BPS GND
L2 R19 600 µH 4.02 kΩ VR1 12.7 kΩ 1 3
CONTROL
VR2 1%
FB
1% DZ2S100M0L MMSZ5259B 10 V F1 RT1 t
O S BPP IS
R21 2 A 5 Ω
InnoSwitch3-CP
0.01 Ω C15 C14 U1 1%
85 - 265
4.7 µF 22 µF INN3268C-H208
VAC
50 V 50 V
RTN J1 J2
*Not connected PI-8409a-090717 Figure 11. 5 V, 3 A ; 9 V, 3 A ; 15 V, 3 A USB PD 2.0 Compliant Adapter. The circuit shown in Figure 11 is a 5 V, 3 A ; 9 V, 3 A ; 15 V, 3 A USB The secondary-side control er of the InnoSwitch3-CP IC provides PD 2.0 compliant adapter using INN3268C. This design is DOE Level output voltage sensing and output current sensing as well as driving 6 and EC CoC 5 compliant. the synchronous rectification FET. The secondary output from the transformer is rectified by FET Q3 and filtered by capacitors C6 and Common mode chokes L1 and L2 provide attenuation for EMI. Bridge C7. High frequency ringing during switching transients that would rectifiers BR1 and BR2 rectify the AC line voltage and provide a full otherwise create radiated EMI is reduced via an RC snubber, R8 and C8. wave rectified DC. Thermistor RT1 limits the inrush current when the power supply is connected to the input AC supply. Fuse F1 isolates The gate of Q3 is turned on by the secondary-side control er inside the circuit and provides protection from component failure. U1, based on the voltage (sensed via resistor R13) fed to the FORWARD pin of the IC. One end of the transformer primary is connected to the rectified DC bus; the other is connected to the drain terminal of the integrated In continuous conduction mode, the FET is turned off prior to the Switch in the InnoSwitch3-CP IC (U1). secondary-side’s requesting the start of a new switching cycle from the primary. The power FET is turned off when the voltage drop A low cost RCD clamp formed by diode D1, resistors R2 and R5 and across the FET fal s below a threshold of V . Secondary-side SR(TH) capacitor C4 limits the peak drain voltage of U1 at the instant of turn control of the primary-side power switch avoids any possibility of off of the Switch inside U1. The clamp helps to dissipate the energy cross conduction of the two Switchs and provides extremely reliable stored in the leakage reactance of transformer T1. synchronous rectification. The InnoSwitch3-CP IC is self-starting, using an internal high-voltage The secondary-side of the IC is self-powered from either the output current source to charge the PRIMARY BYPASS pin capacitor (C15) winding forward voltage or the output voltage. Capacitor C10, when AC is first applied. During normal operation, the primary-side connected to the SECONDARY BYPASS pin of IC U1 provides block is powered from an auxiliary winding on the transformer T1. decoupling for the internal circuitry. Output of the auxiliary (or bias) winding is rectified using diode D3 and filtered using capacitor C14. Resistors R15 and R20 along with During CC operation, when the output voltage fal s, the device will Q7 and VR2 form a linear regulator circuit to control the current directly power itself from the secondary winding. During the on-time supplied to the PRIMARY BYPASS pin of U1 irrespective of the output of the primary-side power switch, the forward voltage that appears voltage. The Zener VR1 along with resistor R14 and diode D2 provide across the secondary winding is used to charge the decoupling a latching OVP in the event of an output overvoltage condition. capacitor C10 via resistor R13 and an internal regulator. This al ows output current regulation to be maintained down to ~3.4 V. Output In a flyback converter, output of the auxiliary winding tracks the current is sensed by monitoring the voltage drop across resistor R21 output voltage of the converter. In the event of an overvoltage on between the IS and SECONDARY GROUND pins. A threshold of the output of the converter, the auxiliary winding voltage increases approximately 35 mV reduces losses. Once the internal current sense and causes VR1 to breakdown. This puts current into the PRIMARY threshold is exceeded the device regulates the number of switch BYPASS pin of U1. If the current into the PRIMARY BYPASS pin pulses to maintain a fixed output current. increases above the I threshold, the InnoSwitch3-CP control er will SD latch-off, preventing any further increase in output voltage.
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Rev. E 07/19 www.power.com Document Outline Product Highlights Description Output Power Table Pin Functional Description InnoSwitch3-CP Functional Description Primary Controller Secondary Controller Applications Example Key Application Considerations Selection of Components Recommendations for Circuit Board Layout Layout Example Quick Design Checklist Absolute Maximum Ratings Thermal Resistance Typical Performance Curves InSOP-24D Package Drawing InSOP-24D Package Marking Part Ordering Table MSL Table ESD and Latch-Up Table Part Ordering Information