Datasheet ADL5202 (Analog Devices) - 6

ADL5202 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 0 A A / / A A _ _ K T L 2 C DA A _ _ / HA – + PA A– A+ A C U _ DN DN T D UT UT A P P INA INA N O O F U U LA V V PW G V V 0 9 8 7 6 5 4 3 2 1 4 3 3 3 3 3 3 3 3 3 PIN 1 1 INDICATOR CSA/A3 30 VOUTA– A4 2 29 VOUTA+ A5 3 28 VPOS MODE1 4 ADL5202 27 VPOS MODE0 5 26 VPOS TOP VIEW PM 6 25 VPOS (Not to Scale) GND 7 24 VPOS SIDO/B5 8 EXPOSED 23 VPOS PADDLE SCLK/B4 9 22 VOUTB+ GS1/CSB/B3 10 21 VOUTB– 2 3 4 5 6 7 8 9 0 11 1 1 1 1 1 1 1 1 2 2 1 0 – + D – + B/ B/ B/ PB N B B B B B CHB INB U INB G T T _ _ _ V V U U A K T W AT P O O /F L L V V 0 C DA S _ _ G DN DN P P U U NOTES
003
1. THE EXPOSED PADDLE (EP) MUST BE CONNECTED TO A LOW IMPEDANCE GROUND PAD.
09387- Figure 5. Pin Configuration
Table 3. Pin Function Descriptions Pin No. Mnemonic Description
1 CSA/A3 Channel A Select (CSA). When serial mode is enabled, a logic low (0 V ≤ CSA ≤ 0.8 V) selects Channel A. Bit 3 for Channel A Parallel Gain Control Interface (A3). 2 A4 Bit 4 for Channel A Parallel Gain Control Interface. 3 A5 Bit 5 (MSB) for Channel A Parallel Gain Control Interface. 4 MODE1 MSB for Mode Control. With the MODE0 pin, selects parallel, SPI, or up/down interface mode. 5 MODE0 LSB for Mode Control. With the MODE1 pin, selects parallel, SPI, or up/down interface mode. 6 PM Performance Mode. A logic low (0 V ≤ PM ≤ 0.8 V) enables high performance mode. A logic high (2.8 V ≤ PM ≤ 3.3 V) enables low power mode. 7, 18, 33, EP GND Ground. The exposed paddle (EP) must be connected to a low impedance ground pad. 8 SDIO/B5 Serial Data Input/Output (SDIO). When CSA or CSB is pulled low, SDIO is used for reading and writing to the SPI port. Bit 5 for Channel B Parallel Gain Control Interface (B5). 9 SCLK/B4 Serial Clock Input in SPI Mode (SCLK). Bit 4 for Channel B Parallel Gain Control Interface (B4). 10 GS1/CSB/B3 MSB for Gain Step Size Control in Up/Down Mode (GS1). Channel B Select (CSB). When serial mode is enabled, a logic low (0 V ≤ CSB≤ 0.8 V) selects Channel B. Bit 3 for Channel B Parallel Gain Control Interface (B3). 11 GS0/FA_B/B2 LSB for Gain Step Size Control in Up/Down Mode (GS0). Fast Attack (FA_B). In serial mode, a logic high (1.4 V ≤ FA_B ≤ 3.3 V) attenuates Channel B according to the FA setting in the SPI word. Bit 2 for Channel B Parallel Gain Control Interface (B2). 12 UPDN_CLK_B/B1 Clock Interface for Channel B Up/Down Function (UPDN_CLK_B). Bit 1 for Channel B Parallel Gain Control Interface (B1). 13 UPDN_DAT_B/B0 Data Pin for Channel B Up/Down Function (UPDN_DAT_B). Bit 0 for Channel B Parallel Gain Control Interface (B0). 14 LATCHB Channel B Latch. A logic low (0 V ≤ LATCHB ≤ 0.8 V) allows gain changes on Channel B. A logic high (1.4 V ≤ LATCHB ≤ 3.3 V) prevents gain changes on Channel B. Rev. D | Page 6 of 29 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS CHARACTERIZATION AND TEST CIRCUITS THEORY OF OPERATION DIGITAL INTERFACE OVERVIEW PARALLEL DIGITAL INTERFACE SERIAL PERIPHERAL INTERFACE (SPI) Fast Attack GAIN UP/DOWN INTERFACE TRUTH TABLE LOGIC TIMING CIRCUIT DESCRIPTION BASIC STRUCTURE Input System Output Amplifier Gain Control APPLICATIONS INFORMATION BASIC CONNECTIONS ADC DRIVING LAYOUT CONSIDERATIONS EVALUATION BOARD EVALUATION BOARD CONTROL SOFTWARE EVALUATION BOARD SCHEMATICS AND ARTWORK EVALUATION BOARD CONFIGURATION OPTIONS Configuration Options for the Main Section Configuration Options for the USB Section OUTLINE DIMENSIONS ORDERING GUIDE