Datasheet ADL5202 (Analog Devices)

Wide Dynamic Range, High Speed, Digital y Control ed VGA Data Sheet ADL5202 FEATURES FUNCTIONAL BLOCK DIAGRAM Dual independent, digitally controlled VGAs SIDE A SPI WITH FA, −11.5 dB to +20 dB gain range PARALLEL WITH LATCH, UP/DN PWUPA VPOS 0.5 dB ±0.1 dB step size 150 Ω differential input and output 7.5 dB noise figure at maximum gain LOGIC OIP3 > 47.5 dBm at 200 MHz VOUTA+ −3 dB upper frequency bandwidth of 700 MHz VINA+ 0dB TO 31.5dB 150Ω +20dB 150Ω Multiple control interface options VINA– VOUTA– Parallel 6-bit control interface (with latch) MODE0, MODE1 CONTROL Serial peripheral interface (SPI) (with fast attack) CIRCUITRY PM Gain up/down mode Wide input dynamic range VINB+ VOUTB+ 0dB TO 31.5dB 150Ω +20dB 150Ω Low power mode option VINB– VOUTB– Power-down control LOGIC Single 5 V supply operation ADL5202 40-lead, 6 mm × 6 mm LFCSP package PWUPB GND SIDE B APPLICATIONS
001
SPI WITH FA, PARALLEL WITH LATCH,
09387-
Differential ADC drivers UP/DN High IF sampling receivers
Figure 1.
High output power IF amplification Instrumentation GENERAL DESCRIPTION
The ADL5202 is a digitally controlled, variable gain, wide band- The ADL5202 is powered on by applying the appropriate logic width amplifier that provides precise gain control, high output level to the PWUPx pins. The quiescent current of the ADL5202 IP3, and low noise figure. The excellent distortion performance is typical y 160 mA in low power mode. When configured in high and high signal bandwidth make the ADL5202 an excellent gain performance mode for more demanding applications, the quiescent control device for a variety of receiver applications. The ADL5202 current is 210 mA. When powered down, the ADL5202 consumes also incorporates a low power mode option that lowers the supply less than 14 mA and offers excellent input-to-output isolation. current. The gain setting is preserved during power-down. For wide input dynamic range applications, the ADL5202 Fabricated on an Analog Devices, Inc., high speed SiGe process, provides a broad 31.5 dB gain range with 0.5 dB resolution. The the ADL5202 provides precise gain adjustment capabilities with gain is adjustable through multiple gain control interface options: good distortion performance and low phase error. The ADL5202 parallel, serial peripheral interface, and up/down. amplifier comes in a compact, thermally enhanced 40-lead, Incorporating proprietary distortion cancel ation techniques, 6 mm
×
6 mm LFCSP package and operates over a temperature the ADL5202 achieves a better than 47.5 dBm output IP3 at range of −40°C to +85°C. frequencies approaching 200 MHz for most gain settings.
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Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS CHARACTERIZATION AND TEST CIRCUITS THEORY OF OPERATION DIGITAL INTERFACE OVERVIEW PARALLEL DIGITAL INTERFACE SERIAL PERIPHERAL INTERFACE (SPI) Fast Attack GAIN UP/DOWN INTERFACE TRUTH TABLE LOGIC TIMING CIRCUIT DESCRIPTION BASIC STRUCTURE Input System Output Amplifier Gain Control APPLICATIONS INFORMATION BASIC CONNECTIONS ADC DRIVING LAYOUT CONSIDERATIONS EVALUATION BOARD EVALUATION BOARD CONTROL SOFTWARE EVALUATION BOARD SCHEMATICS AND ARTWORK EVALUATION BOARD CONFIGURATION OPTIONS Configuration Options for the Main Section Configuration Options for the USB Section OUTLINE DIMENSIONS ORDERING GUIDE