Datasheet ADRF6518 (Analog Devices) - 7

Data Sheet ADRF6518 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS L G 1 1 B 1 1 S V N S S N P M P A G F P E NI NI V R V O V 32 31 30 29 28 27 26 25 VPSD 1 24 OPP1 COMD 2 23 OPM1 LE 3 22 COM ADRF6518 CLK 4 21 VGN3 DATA TOP VIEW 5 20 VOCM (Not to Scale) SDO/RST 6 19 COM VICM/AC 7 18 OPM2 VPI 8 17 OPP2 9 10 11 12 13 14 15 16 M 2 2 S K 2 2 S O P M P P N S P C NI N F I V V G V V O NOTES 1. CONNECT THE EXPOSED PADDLE TO
-004
A LOW IMPEDANCE GROUND PAD.
1449 1 Figure 4. Pin Configuration
Table 3. Pin Function Descriptions Pin No. Mnemonic Description
1 VPSD Digital Positive Supply Voltage: 3.15 V to 3.45 V. 2 COMD Digital Common. Connect this pin to an external circuit common using the lowest possible impedance. 3 LE Latch Enable. SPI programming pin. TTL levels: VLOW < 0.8 V, VHIGH > 2 V. 4 CLK SPI Port Clock. TTL levels: VLOW < 0.8 V, VHIGH > 2 V. 5 DATA SPI Data Input. TTL levels: VLOW < 0.8 V, VHIGH > 2 V. 6 SDO/RST SPI Data Output (SDO). TTL levels: VLOW < 0.8 V, VHIGH > 2 V. Peak Detector Reset (RST). A >25 ns high pulse is required on this pin to reset the detector. 7 VICM/AC Input Common-Mode Reference (VICM). VPI/2 reference output for optimal common-mode level to drive the differential inputs. If this pin is used as a common-mode reference for the common- mode output of the previous stage, only connect high impedance nodes to this pin. AC Coupling/Internal Bias Activation (AC). Pull this pin low for ac coupling of the inputs. 8 VPI Input Stage Supply Voltage: 3.15 V to 5.25 V. Connect VPI to VPS if the input common-mode range is narrow (1.35 V to 1.95 V). Connect VPI to 5 V if a common-mode input up to 3.1 V is desired. 9, 19, 22 COM Analog Common. Connect COM to an external circuit common using the lowest possible impedance. 10, 11, 30, 31 INP2, INM2, Differential Inputs, 400 Ω Differential Input Impedance. INM1, INP1 12, 16, 25, 29 VPS Analog Positive Supply Voltage: 3.15 V to 3.45 V. 13 VPK Peak Detector Output. Scaling of 1 V/V peak differential at filter inputs is performed, and the bigger peak of two channels is reported. 14, 21, 27 VGN2, VGN3, VGA1, VGA2, and VGA3 Analog Gain Control. 0 V to 1 V, 30 mV/dB gain scaling. VGN1 15, 26 OFS2, OFS1 Offset Correction Loop Compensation Capacitors. Connect capacitors to a circuit common. 17, 18, 23, 24 OPP2, OPM2, Differential Outputs. These outputs have a <10 Ω output impedance. Common-mode range is 0.9 OPM1, OPP1 V to VPS − 1.2 V; default is VPS/2. 20 VOCM Output Common-Mode Setpoint. VOCM defaults to VPS/2 if left open. 28 RAVG Peak Detector Time-Constant Resistor. Connect this pin to VPS. Leave this pin open for the longest hold time. The RAVG range is ∞ to 1 kΩ. 32 ENBL Chip Enable. Pull this pin high to enable the chip. EP Exposed Ground Pad. Connect the exposed pad to a low impedance ground pad. Rev. A | Page 7 of 39 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS FILTER MODE BYPASS MODE MIXED POWER AND FILTER MODES CHARACTERIZATION NOISE FIGURE CALCULATION REGISTER MAP AND CODES THEORY OF OPERATION INPUT VGAs Driving ADRF6518 Single-Ended PEAK DETECTOR PROGRAMMABLE FILTERS Bypassing the Filters VARIABLE GAIN AMPLIFIERS (VGAs) OUTPUT BUFFERS/ADC DRIVERS DC OFFSET COMPENSATION LOOP PROGRAMMING THE ADRF6518 NOISE CHARACTERISTICS DISTORTION CHARACTERISTICS MAXIMIZING THE DYNAMIC RANGE KEY PARAMETERS FOR QUADRATURE-BASED RECEIVERS APPLICATIONS INFORMATION BASIC CONNECTIONS SUPPLY DECOUPLING INPUT SIGNAL PATH OUTPUT SIGNAL PATH DC OFFSET COMPENSATION LOOP ENABLED COMMON-MODE BYPASSING SERIAL PORT CONNECTIONS ENABLE/DISABLE FUNCTION GAIN PIN DECOUPLING PEAK DETECTOR CONNECTIONS ERROR VECTOR MAGNITUDE (EVM) PERFORMANCE EVM TEST SETUP EVM MEASUREMENT EVM SYSTEM MEASUREMENT EFFECT OF FILTER BW ON EVM PULL-DOWN RESISTORS FOR DISABLE FUNCTION INSTABILITY AT HIGH GAIN IN FILTER BYPASS MODE INSTABILITY AT LOW FILTER CORNERS AND LOW POWER MODE PEAK DETECTOR BANDWIDTH AND SLEW RATE LINEAR OPERATION OF THE ADRF6518 EVALUATION BOARD EVALUATION BOARD CONTROL SOFTWARE SCHEMATICS AND ARTWORK OUTLINE DIMENSIONS ORDERING GUIDE