Datasheet ADRF6518 (Analog Devices) - 9

Data Sheet ADRF6518 60 15 50 10 DIGITAL GAIN = 0000001 40 5 30 DIGITAL GAIN = 111110 0 20 ) ) V B B d 10 –5 ( (d IN B 0 d –10 GA –10 OP1 –15 –20 –20 –30 –40 –25 –50 –30 5 15 25 35 45 55 65 75
1 1
–10 0 10 20 30 40 50
014 -0 9-
FREQUENCY (MHz) GAIN (dB)
1449 1144 1 Figure 11. Gain vs. Frequency over VGN1/VGN2/VGN3 Figure 14. OP1dB vs. Gain at a Fundamental of 16 MHz
0 –30 +85°C, VPS = 3.15V, 3.3V, 3.45V +25°C, VPS = 3.15V, 3.3V, 3.45V –5 –40°C, VPS = 3.15V, 3.3V, 3.45V DIGITAL GAIN = 0000001 –10 –35 DIGITAL GAIN = 0000000 –15 DIGITAL GAIN = 0000010 ) ) B DIGITAL GAIN = 0000100 B d –20 d ( DIGITAL GAIN = 0000110 ( IN –40 IN –25 DIGITAL GAIN = 0001110 GA GA DIGITAL GAIN = 0010110 –30 DIGITAL GAIN = 0011110 DIGITAL GAIN = 0111110 –45 –35 DIGITAL GAIN = 1111110 –40 –45 –50 5 10 15 20 25 30 35 40 45 50 55 60
012
3 13 23 33 43 53 63 73 83 93 103
015 9-
FREQUENCY (MHz) FREQUENCY (MHz)
11449- 1144 Figure 12. Digital Gain vs. Frequency; VGN1/VGN2/VGN3 = 0 V Figure 15. Frequency Response over Supply and Temperature; VGN1/VGN2/VGN3 = 0 V, Filter Corners = 15 MHz, 30 MHz, and 60 MHz
0.3 40 35 0.2 30 ) B 25 d 0.1 ( H ) 20 C B T d A ( 0 M 15 IN IS M GA 10 IN A –0.1 G 5 0 –0.2 –5 –0.3 –10 /0 0 0 0 0 /0 0 0 0 0 /0 2 4 6 8 /1 0
016
/0/ /0/ /0/ /0/ 0 .2/ .4/ .6/ .8/ 1 /0. /0. /0. /0. 1 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 0/ 2 4 6 8 1/ 0 0 0 0 1/ 1 1 1 1 1/
9- 013
0. 0. 0. 0. 1/ 1/ 1/ 1/ 1/ 1/ 1/ 1/
9-
FREQUENCY (MHz)
1144
VGN1/VGN2/VGN3 (V)
1144 Figure 13. Gain Mismatch Between Channels vs. VGN1/VGN2/VGN3 Voltage Figure 16. Gain vs. Frequency over BW Setting (Linear); VGN1/VGN2/VGN3 = 0 V Rev. A | Page 9 of 39 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS FILTER MODE BYPASS MODE MIXED POWER AND FILTER MODES CHARACTERIZATION NOISE FIGURE CALCULATION REGISTER MAP AND CODES THEORY OF OPERATION INPUT VGAs Driving ADRF6518 Single-Ended PEAK DETECTOR PROGRAMMABLE FILTERS Bypassing the Filters VARIABLE GAIN AMPLIFIERS (VGAs) OUTPUT BUFFERS/ADC DRIVERS DC OFFSET COMPENSATION LOOP PROGRAMMING THE ADRF6518 NOISE CHARACTERISTICS DISTORTION CHARACTERISTICS MAXIMIZING THE DYNAMIC RANGE KEY PARAMETERS FOR QUADRATURE-BASED RECEIVERS APPLICATIONS INFORMATION BASIC CONNECTIONS SUPPLY DECOUPLING INPUT SIGNAL PATH OUTPUT SIGNAL PATH DC OFFSET COMPENSATION LOOP ENABLED COMMON-MODE BYPASSING SERIAL PORT CONNECTIONS ENABLE/DISABLE FUNCTION GAIN PIN DECOUPLING PEAK DETECTOR CONNECTIONS ERROR VECTOR MAGNITUDE (EVM) PERFORMANCE EVM TEST SETUP EVM MEASUREMENT EVM SYSTEM MEASUREMENT EFFECT OF FILTER BW ON EVM PULL-DOWN RESISTORS FOR DISABLE FUNCTION INSTABILITY AT HIGH GAIN IN FILTER BYPASS MODE INSTABILITY AT LOW FILTER CORNERS AND LOW POWER MODE PEAK DETECTOR BANDWIDTH AND SLEW RATE LINEAR OPERATION OF THE ADRF6518 EVALUATION BOARD EVALUATION BOARD CONTROL SOFTWARE SCHEMATICS AND ARTWORK OUTLINE DIMENSIONS ORDERING GUIDE