Datasheet AD9271 (Analog Devices) - 2
| Hersteller | Analog Devices |
| Beschreibung | Octal LNA/VGA/AAF/ADC and Crosspoint Switch |
| Seiten / Seite | 60 / 2 — AD9271. TABLE OF CONTENTS. REVISION HISTORY. 5/09—Rev. A to Rev. B. … |
| Revision | B |
| Dateiformat / Größe | PDF / 2.1 Mb |
| Dokumentensprache | Englisch |
AD9271. TABLE OF CONTENTS. REVISION HISTORY. 5/09—Rev. A to Rev. B. 12/07—Rev. 0 to Rev. A. 6/07—Revision 0: Initial Version
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AD9271 TABLE OF CONTENTS
Features .. 1 TGC Operation ... 25 Applications ... 1 ADC ... 27 General Description ... 1 Clock Input Considerations .. 28 Functional Block Diagram .. 1 Serial Port Interface (SPI) .. 35 Revision History ... 2 Hardware Interface ... 35 Product Highlights ... 3 Memory Map .. 37 Specifications ... 4 Reading the Memory Map Table .. 37 AC Specifications .. 4 Reserved Locations .. 37 Digital Specifications ... 7 Default Values ... 37 Switching Specifications .. 8 Logic Levels ... 37 ADC Timing Diagrams ... 9 Applications Information .. 41 Absolute Maximum Ratings .. 10 Design Guidelines .. 41 Thermal Impedance ... 10 Evaluation Board .. 42 ESD Caution .. 10 Power Supplies .. 42 Pin Configuration and Function Descriptions ... 11 Input Signals.. 42 Equivalent Circuits ... 14 Output Signals .. 42 Typical Performance Characteristics ... 16 Default Operation and Jumper Selection Settings ... 43 Theory of Operation .. 20 Quick Start Procedure ... 44 Ultrasound ... 20 Schematics and Artwork ... 45 Channel Overview .. 21 Outline Dimensions ... 58 Input Overdrive .. 23 Ordering Guide .. 58 CW Doppler Operation ... 24
REVISION HISTORY 5/09—Rev. A to Rev. B
Changes to LNA Noise Section .. 22 Changes to Figure 27 .. 17 Changes to Figure 43 .. 22 Changes to Figure 40 and Figure 41 ... 21 Change to Input Overload Protection Section ... 23 Changes to Ordering Guide .. 58 Changes to TGC Operation Section .. 25 Changes to Gain Control Section ... 26
12/07—Rev. 0 to Rev. A
Changes to Figure 52 .. 26 Change to AC Specifications Text .. 4 Change to Table 11 ... 33 Added Input Noise Current .. 4 Changes to Serial Interface Port (SPI) Section ... 35 Added Noise Figure .. 4 Changes to Hardware Interface Section .. 35 Changes to Signal-to-Noise Ratio Units .. 4 Changes to Reading the Memory Map Table Section ... 37 Changes to Harmonic Distortion Units .. 5 Added Applications Information and Added Endnote 3 .. 6 Design Guidelines Sections .. 41 Changes to Table 6 .. 11 Change to Input Signals Section ... 42 Inserted Figure 19 and Figure 21 .. 16 Changes to Figure 73 .. 42 Changes to Figure 20 .. 16 Changes to Table 16 ... 55 Changes to Theory of Operation Section .. 20
6/07—Revision 0: Initial Version
Changes to Figure 40 and Figure 41 ... 21 Change to Active Impedance Matching Section .. 22 Rev. B | Page 2 of 60 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY PRODUCT HIGHLIGHTS SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS ADC TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL IMPEDANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS EQUIVALENT CIRCUITS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION ULTRASOUND CHANNEL OVERVIEW Low Noise Amplifier (LNA) Active Impedance Matching LNA Noise INPUT OVERDRIVE Input Overload Protection CW DOPPLER OPERATION Crosspoint Switch TGC OPERATION Variable Gain Amplifier Gain Control VGA Noise Antialiasing Filter ADC CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Clock Jitter Considerations Power Dissipation and Power-Down Mode Digital Outputs and Timing SDIO Pin SCLK Pin CSB Pin RBIAS Pin Voltage Reference Internal Reference Operation External Reference Operation SERIAL PORT INTERFACE (SPI) HARDWARE INTERFACE MEMORY MAP READING THE MEMORY MAP TABLE RESERVED LOCATIONS DEFAULT VALUES LOGIC LEVELS APPLICATIONS INFORMATION DESIGN GUIDELINES Power and Ground Recommendations Exposed Paddle Thermal Heat Slug Recommendations EVALUATION BOARD POWER SUPPLIES INPUT SIGNALS OUTPUT SIGNALS DEFAULT OPERATION AND JUMPER SELECTION SETTINGS QUICK START PROCEDURE SCHEMATICS AND ARTWORK OUTLINE DIMENSIONS ORDERING GUIDE
AD9271 TABLE OF CONTENTS
Features .. 1 TGC Operation ... 25 Applications ... 1 ADC ... 27 General Description ... 1 Clock Input Considerations .. 28 Functional Block Diagram .. 1 Serial Port Interface (SPI) .. 35 Revision History ... 2 Hardware Interface ... 35 Product Highlights ... 3 Memory Map .. 37 Specifications ... 4 Reading the Memory Map Table .. 37 AC Specifications .. 4 Reserved Locations .. 37 Digital Specifications ... 7 Default Values ... 37 Switching Specifications .. 8 Logic Levels ... 37 ADC Timing Diagrams ... 9 Applications Information .. 41 Absolute Maximum Ratings .. 10 Design Guidelines .. 41 Thermal Impedance ... 10 Evaluation Board .. 42 ESD Caution .. 10 Power Supplies .. 42 Pin Configuration and Function Descriptions ... 11 Input Signals.. 42 Equivalent Circuits ... 14 Output Signals .. 42 Typical Performance Characteristics ... 16 Default Operation and Jumper Selection Settings ... 43 Theory of Operation .. 20 Quick Start Procedure ... 44 Ultrasound ... 20 Schematics and Artwork ... 45 Channel Overview .. 21 Outline Dimensions ... 58 Input Overdrive .. 23 Ordering Guide .. 58 CW Doppler Operation ... 24
REVISION HISTORY 5/09—Rev. A to Rev. B
Changes to LNA Noise Section .. 22 Changes to Figure 27 .. 17 Changes to Figure 43 .. 22 Changes to Figure 40 and Figure 41 ... 21 Change to Input Overload Protection Section ... 23 Changes to Ordering Guide .. 58 Changes to TGC Operation Section .. 25 Changes to Gain Control Section ... 26
12/07—Rev. 0 to Rev. A
Changes to Figure 52 .. 26 Change to AC Specifications Text .. 4 Change to Table 11 ... 33 Added Input Noise Current .. 4 Changes to Serial Interface Port (SPI) Section ... 35 Added Noise Figure .. 4 Changes to Hardware Interface Section .. 35 Changes to Signal-to-Noise Ratio Units .. 4 Changes to Reading the Memory Map Table Section ... 37 Changes to Harmonic Distortion Units .. 5 Added Applications Information and Added Endnote 3 .. 6 Design Guidelines Sections .. 41 Changes to Table 6 .. 11 Change to Input Signals Section ... 42 Inserted Figure 19 and Figure 21 .. 16 Changes to Figure 73 .. 42 Changes to Figure 20 .. 16 Changes to Table 16 ... 55 Changes to Theory of Operation Section .. 20
6/07—Revision 0: Initial Version
Changes to Figure 40 and Figure 41 ... 21 Change to Active Impedance Matching Section .. 22 Rev. B | Page 2 of 60 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY PRODUCT HIGHLIGHTS SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS ADC TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL IMPEDANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS EQUIVALENT CIRCUITS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION ULTRASOUND CHANNEL OVERVIEW Low Noise Amplifier (LNA) Active Impedance Matching LNA Noise INPUT OVERDRIVE Input Overload Protection CW DOPPLER OPERATION Crosspoint Switch TGC OPERATION Variable Gain Amplifier Gain Control VGA Noise Antialiasing Filter ADC CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Clock Jitter Considerations Power Dissipation and Power-Down Mode Digital Outputs and Timing SDIO Pin SCLK Pin CSB Pin RBIAS Pin Voltage Reference Internal Reference Operation External Reference Operation SERIAL PORT INTERFACE (SPI) HARDWARE INTERFACE MEMORY MAP READING THE MEMORY MAP TABLE RESERVED LOCATIONS DEFAULT VALUES LOGIC LEVELS APPLICATIONS INFORMATION DESIGN GUIDELINES Power and Ground Recommendations Exposed Paddle Thermal Heat Slug Recommendations EVALUATION BOARD POWER SUPPLIES INPUT SIGNALS OUTPUT SIGNALS DEFAULT OPERATION AND JUMPER SELECTION SETTINGS QUICK START PROCEDURE SCHEMATICS AND ARTWORK OUTLINE DIMENSIONS ORDERING GUIDE