Datasheet AD9271 (Analog Devices) - 3

AD9271
The AD9271 requires a LVPECL-/CMOS-/LVDS-compatible Fabricated in an advanced CMOS process, the AD9271 is sample rate clock for full performance operation. No external available in a 16 mm × 16 mm, RoHS compliant, 100-lead reference or driver components are required for many TQFP. It is specified over the industrial temperature range of applications. −40°C to +85°C. The ADC automatically multiplies the sample rate clock for
PRODUCT HIGHLIGHTS
the appropriate LVDS serial data rate. A data clock (DCO±) for 1. Small Footprint. Eight channels are contained in a small, capturing data on the output and a frame clock (FCO±) trigger space-saving package. Full TGC path, ADC, and crosspoint for signaling a new output byte are provided. switch contained within a 100-lead, 16 mm × 16 mm TQFP. Powering down individual channels is supported to increase 2. Low Power of 150 mW per Channel at 40 MSPS. battery life for portable applications. There is also a standby 3. Integrated Crosspoint Switch. This switch allows numerous mode option that allows quick power-up for power cycling. In CW multichannel configuration options to enable the CW Doppler operation, the VGA, AAF, and ADC are powered down. Doppler mode. The power of the TGC path scales with selectable speed grades. 4. Ease of Use. A data clock output (DCO±) operates up to The ADC contains several features designed to maximize flexibility 300 MHz and supports double data rate (DDR) operation. and minimize system cost, such as a programmable clock, data 5. User Flexibility. Serial port interface (SPI) control offers a wide alignment, and programmable digital test pattern generation. The range of flexible features to meet specific system requirements. digital test patterns include built-in fixed patterns, built-in 6. Integrated Third-Order Antialiasing Filter. This filter is placed pseudorandom patterns, and custom user-defined test patterns between the TGC path and the ADC and is programmable entered via the serial port interface. from 8 MHz to 18 MHz. Rev. B | Page 3 of 60 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY PRODUCT HIGHLIGHTS SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS ADC TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL IMPEDANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS EQUIVALENT CIRCUITS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION ULTRASOUND CHANNEL OVERVIEW Low Noise Amplifier (LNA) Active Impedance Matching LNA Noise INPUT OVERDRIVE Input Overload Protection CW DOPPLER OPERATION Crosspoint Switch TGC OPERATION Variable Gain Amplifier Gain Control VGA Noise Antialiasing Filter ADC CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Clock Jitter Considerations Power Dissipation and Power-Down Mode Digital Outputs and Timing SDIO Pin SCLK Pin CSB Pin RBIAS Pin Voltage Reference Internal Reference Operation External Reference Operation SERIAL PORT INTERFACE (SPI) HARDWARE INTERFACE MEMORY MAP READING THE MEMORY MAP TABLE RESERVED LOCATIONS DEFAULT VALUES LOGIC LEVELS APPLICATIONS INFORMATION DESIGN GUIDELINES Power and Ground Recommendations Exposed Paddle Thermal Heat Slug Recommendations EVALUATION BOARD POWER SUPPLIES INPUT SIGNALS OUTPUT SIGNALS DEFAULT OPERATION AND JUMPER SELECTION SETTINGS QUICK START PROCEDURE SCHEMATICS AND ARTWORK OUTLINE DIMENSIONS ORDERING GUIDE