Datasheet AD9266-EP (Analog Devices) - 6
| Hersteller | Analog Devices |
| Beschreibung | 16-Bit, 20/40/65/80 MSPS, 1.8 V Analog-to-Digital Converter |
| Seiten / Seite | 12 / 6 — AD9266-EP. Enhanced Product. DIGITAL SPECIFICATIONS. Table 3. Parameter. … |
| Revision | B |
| Dateiformat / Größe | PDF / 241 Kb |
| Dokumentensprache | Englisch |
AD9266-EP. Enhanced Product. DIGITAL SPECIFICATIONS. Table 3. Parameter. Temp. Min. Typ. Max. Unit
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AD9266-EP Enhanced Product DIGITAL SPECIFICATIONS
AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle clock, DCS disabled, unless otherwise noted.
Table 3. Parameter Temp Min Typ Max Unit
DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−) Logic Compliance CMOS/LVDS/LVPECL Internal Common-Mode Bias Full 0.9 V Differential Input Voltage Full 0.2 3.6 V p-p Input Voltage Range Full GND − 0.3 AVDD + 0.2 V High Level Input Current Full −10 +10 µA Low Level Input Current Full −10 +10 µA Input Resistance Full 8 10 12 kΩ Input Capacitance Full 4 pF LOGIC INPUTS (SCLK/DFS, MODE, SDIO/PDWN)1 High Level Input Voltage Full 1.2 DRVDD + 0.3 V Low Level Input Voltage Full 0 0.8 V High Level Input Current Full −50 −75 µA Low Level Input Current Full −10 +10 µA Input Resistance Full 30 kΩ Input Capacitance Full 2 pF LOGIC INPUTS (CSB)2 High Level Input Voltage Full 1.2 DRVDD + 0.3 V Low Level Input Voltage Full 0 0.8 V High Level Input Current Full −10 +10 µA Low Level Input Current Full 40 135 µA Input Resistance Full 26 kΩ Input Capacitance Full 2 pF DIGITAL OUTPUTS DRVDD = 3.3 V High Level Output Voltage, IOH = 50 µA Full 3.29 V High Level Output Voltage, IOH = 0.5 mA Full 3.25 V Low Level Output Voltage, IOL = 1.6 mA Full 0.2 V Low Level Output Voltage, IOL = 50 µA Full 0.05 V DRVDD = 1.8 V High Level Output Voltage, IOH = 50 µA Full 1.79 V High Level Output Voltage, IOH = 0.5 mA Full 1.75 V Low Level Output Voltage, IOL = 1.6 mA Full 0.2 V Low Level Output Voltage, IOL = 50 µA Full 0.05 V 1 Internal 30 kΩ pull-down. 2 Internal 30 kΩ pull-up. Rev. B | Page 6 of 12 Document Outline FEATURES ENHANCED PRODUCT FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS OUTLINE DIMENSIONS ORDERING GUIDE
AD9266-EP Enhanced Product DIGITAL SPECIFICATIONS
AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle clock, DCS disabled, unless otherwise noted.
Table 3. Parameter Temp Min Typ Max Unit
DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−) Logic Compliance CMOS/LVDS/LVPECL Internal Common-Mode Bias Full 0.9 V Differential Input Voltage Full 0.2 3.6 V p-p Input Voltage Range Full GND − 0.3 AVDD + 0.2 V High Level Input Current Full −10 +10 µA Low Level Input Current Full −10 +10 µA Input Resistance Full 8 10 12 kΩ Input Capacitance Full 4 pF LOGIC INPUTS (SCLK/DFS, MODE, SDIO/PDWN)1 High Level Input Voltage Full 1.2 DRVDD + 0.3 V Low Level Input Voltage Full 0 0.8 V High Level Input Current Full −50 −75 µA Low Level Input Current Full −10 +10 µA Input Resistance Full 30 kΩ Input Capacitance Full 2 pF LOGIC INPUTS (CSB)2 High Level Input Voltage Full 1.2 DRVDD + 0.3 V Low Level Input Voltage Full 0 0.8 V High Level Input Current Full −10 +10 µA Low Level Input Current Full 40 135 µA Input Resistance Full 26 kΩ Input Capacitance Full 2 pF DIGITAL OUTPUTS DRVDD = 3.3 V High Level Output Voltage, IOH = 50 µA Full 3.29 V High Level Output Voltage, IOH = 0.5 mA Full 3.25 V Low Level Output Voltage, IOL = 1.6 mA Full 0.2 V Low Level Output Voltage, IOL = 50 µA Full 0.05 V DRVDD = 1.8 V High Level Output Voltage, IOH = 50 µA Full 1.79 V High Level Output Voltage, IOH = 0.5 mA Full 1.75 V Low Level Output Voltage, IOL = 1.6 mA Full 0.2 V Low Level Output Voltage, IOL = 50 µA Full 0.05 V 1 Internal 30 kΩ pull-down. 2 Internal 30 kΩ pull-up. Rev. B | Page 6 of 12 Document Outline FEATURES ENHANCED PRODUCT FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS OUTLINE DIMENSIONS ORDERING GUIDE