Datasheet AD9266-EP (Analog Devices) - 5

Enhanced Product AD9266-EP AC SPECIFICATIONS
AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle clock, DCS disabled, unless otherwise noted.
Table 2. Parameter1 Temp Min Typ Max Unit
SIGNAL-TO-NOISE RATIO (SNR) fIN = 9.7 MHz 25°C 77.6 dBFS fIN = 30.5 MHz 25°C 77.4 dBFS Full 76.5 dBFS fIN = 70 MHz 25°C 76.4 dBFS SIGNAL-TO-NOISE-AND-DISTORTION (SINAD) fIN = 9.7 MHz 25°C 77.4 dBFS fIN = 30.5 MHz 25°C 77.2 dBFS Full 76.0 dBFS fIN = 70 MHz 25°C 76.3 dBFS EFFECTIVE NUMBER OF BITS (ENOB) fIN = 9.7 MHz 25°C 12.6 Bits fIN = 30.5 MHz 25°C 12.5 Bits Full 12.3 Bits fIN = 70 MHz 25°C 12.4 Bits WORST SECOND OR THIRD HARMONIC fIN = 9.7 MHz 25°C −94 dBc fIN = 30.5 MHz 25°C −93 dBc Full −80 dBc fIN = 70 MHz 25°C −93 dBc SPURIOUS-FREE DYNAMIC RANGE (SFDR) fIN = 9.7 MHz 25°C 94 dBc fIN = 30.5 MHz 25°C 93 dBc Full 80 dBc fIN = 70 MHz 25°C 93 dBc WORST OTHER (HARMONIC OR SPUR) fIN = 9.7 MHz 25°C −92 dBc fIN = 30.5 MHz 25°C −101 dBc Full −88 dBc fIN = 70 MHz 25°C −98 dBc TWO-TONE SFDR fIN = 30.5 MHz (−7 dBFS), 32.5 MHz (−7 dBFS) 25°C 90 dBc ANALOG INPUT BANDWIDTH 25°C 700 MHz 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions. Rev. B | Page 5 of 12 Document Outline FEATURES ENHANCED PRODUCT FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS OUTLINE DIMENSIONS ORDERING GUIDE