Datasheet AD9697 (Analog Devices) - 4

AD9697 Data Sheet GENERAL DESCRIPTION
The AD9697 is a single, 14-bit, 1300 MSPS analog-to-digital an overrange condition at the ADC input. In addition to the fast converter (ADC). The device has an on-chip buffer and a sample- detect outputs, the AD9697 also offers signal monitoring and-hold circuit designed for low power, small size, and ease capability. The signal monitoring block provides additional of use. This product is designed to support communications information about the signal being digitized by the ADC. applications capable of direct sampling wide bandwidth analog The user can configure the Subclasss 1 JESD204B-based high signals of up to 2 GHz. The −3 dB bandwidth of the ADC input speed serialized output using either one lane, two lanes, or four is 2 GHz. The AD9697 is optimized for wide input bandwidth, lanes, depending on the DDC configuration and the acceptable high sampling rate, excellent linearity, and low power in a small lane rate of the receiving logic device. Multidevice synchronization package. is supported through the SYSREF± and SYNCINB± input pins. The ADC core features a multistage, differential pipelined The AD9697 has flexible power-down options that al ow architecture with integrated output error correction logic. The significant power savings when desired. All of these features can ADC features wide bandwidth inputs supporting a variety of be programmed using a 3-wire SPI and or PDWN/STBY pin. user-selectable input ranges. An integrated voltage reference eases design considerations. The analog input and clock signals The AD9697 is available in a Pb-free, 64-lead LFCSP and is are differential inputs. The ADC data outputs are internal y specified over the −40°C to +105°C junction temperature (TJ) connected to four digital downconverters (DDCs) through a range. This product may be protected by one or more U.S. or crossbar mux. Each DDC consists of multiple signal processing international patents. stages: a 48-bit frequency translator (numerically control ed Note that, throughout this data sheet, a multifunction pin, oscil ator (NCO)), and decimation filters. The NCO has the option FD/GPIO1, is referred to either by the entire pin name or by a to select up to 16 preset bands over the general-purpose input/ single function of the pin, for example, FD, when only that output (GPIO) pins, or to use a coherent fast frequency hopping function is relevant. mechanism for band selection. Operation of the AD9697 between
PRODUCT HIGHLIGHTS
the DDC modes is selectable via serial port interface (SPI)- 1. Low power consumption. programmable profiles. 2. JESD204B lane rate support up to 16 Gbps. In addition to the DDC blocks, the AD9697 has several functions 3. Wide, ful power bandwidth supports intermediate that simplify the automatic gain control (AGC) function in a frequency (IF) sampling of signals up to 2 GHz. communications receiver. The programmable threshold detector 4. Buffered inputs ease filter design and implementation. allows monitoring of the incoming signal power using the fast 5. Four integrated wideband decimation filters and NCO detect control bits in Register 0x0245 of the ADC. If the input blocks supporting multiband receivers. signal level exceeds the programmable threshold, the fast detect 6. Programmable fast overrange detection. indicator goes high. Because this threshold indicator has low 7. On-chip temperature diode for system thermal management. latency, the user can quickly turn down the system gain to avoid Rev. 0 | Page 4 of 130 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION PRODUCT HIGHLIGHTS SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Differential Input Configurations Input Common Mode Analog Input Buffer Controls and SFDR Optimization Absolute Maximum Input Swing Dither VOLTAGE REFERENCE DC OFFSET CALIBRATION CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Input Clock Divider Input Clock Divider ½ Period Delay Adjust Clock Fine Delay and Superfine Delay Adjust Clock Coupling Considerations Clock Jitter Considerations POWER-DOWN/STANDBY MODE TEMPERATURE DIODE ADC OVERRANGE AND FAST DETECT ADC OVERRANGE FAST THRESHOLD DETECTION (FD) ADC APPLICATION MODES AND JESD204B Tx CONVERTER MAPPING PROGRAMMABLE FINITE IMPULSE RESPONSE (FIR) FILTERS SUPPORTED MODES PROGRAMMING INSTRUCTIONS DIGITAL DOWNCONVERTER (DDC) DDC I/Q OUTPUT SELECTION DDC GENERAL DESCRIPTION Frequency Translation Stage (Optional) Filtering Stage Gain Stage (Optional) Complex to Real Conversion Stage (Optional) DDC FREQUENCY TRANSLATION DDC Frequency Translation General Description Variable IF Mode 0 Hz IF (ZIF) Mode fS/4 Hz IF Mode Test Mode DDC NCO Description DDC NCO Programmable Modulus Mode DDC NCO Coherent Mode NCO FTW/POW/MAW/MAB Description NCO FTW/POW/MAW/MAB Programmable Modulus Mode NCO FTW/POW/MAW/MAB Coherent Mode NCO Channel Selection GPIO Level Control Mode GPIO Edge Control Mode Register Map Mode Setting Up the Multichannel NCO Feature NCO Synchronization NCO Multichip Synchronization NCO Multichip Synchronization at Startup NCO Multichip Synchronization During Normal Operation DDC Mixer Description DDC NCO + Mixer Loss and SFDR DDC DECIMATION FILTERS HB4 Filter Description HB3 Filter Description HB2 Filter Description HB1 Filter Description TB2 Filter Description TB1 Filter Description FB2 Filter Description DDC GAIN STAGE DDC COMPLEX TO REAL CONVERSION DDC MIXED DECIMATION SETTINGS DDC EXAMPLE CONFIGURATIONS SIGNAL MONITOR SPORT OVER JESD204B DIGITAL OUTPUTS INTRODUCTION TO THE JESD204B INTERFACE JESD204B OVERVIEW FUNCTIONAL OVERVIEW Transport Layer Data Link Layer Physical Layer JESD204B LINK ESTABLISHMENT Code Group Synchronization (CGS) Initial Lane Alignment Sequence (ILAS) User Data and Error Detection 8-Bit/10-Bit Encoder PHYSICAL LAYER (DRIVER) OUTPUTS Digital Outputs, Timing, and Controls De-Emphasis Phase-Locked Loop (PLL) SETTING UP THE AD9697 DIGITAL INTERFACE Example Setup 1—Full Bandwidth Mode Example Setup 2—ADC with DDC Option (Two ADCs Plus Two DDCs) DETERMINISTIC LATENCY SUBCLASS 0 OPERATION SUBCLASS 1 OPERATION Deterministic Latency Requirements Setting Deterministic Latency Registers MULTICHIP SYNCHRONIZATION NORMAL MODE TIMESTAMP MODE SYSREF± INPUT SYREF± Control Features SYSREF± SETUP/HOLD WINDOW MONITOR LATENCY END TO END TOTAL LATENCY EXAMPLE LATENCY CALCULATIONS LMFC REFERENCED LATENCY TEST MODES ADC TEST MODES JESD204B BLOCK TEST MODES Transport Layer Sample Test Mode Interface Test Modes Data Link Layer Test Modes SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open and Reserved Locations Default Values Logic Levels SPI Soft Reset MEMORY MAP REGISTERS APPLICATIONS INFORMATION POWER SUPPLY RECOMMENDATIONS LAYOUT GUIDELINES AVDD1_SR (PIN 57) AND AGND_SR (PIN 56 AND PIN 60) OUTLINE DIMENSIONS ORDERING GUIDE