Datasheet AD9697 (Analog Devices)

14-Bit, 1300 MSPS, JESD204B, Analog-to-Digital Converter Data Sheet AD9697 FEATURES APPLICATIONS JESD204B (Subclass 1) coded serial digital outputs Communications Lane rates up to 16 Gbps Diversity multiband, multimode digital receivers Total power dissipation: 1.00 W at 1300 MSPS 3G/4G, TD-SCDMA, W-CDMA, GSM, LTE SNR: 65.6 dBFS at 172.3 MHz (1.59 V p-p analog input full scale) General-purpose software radios SFDR: 78 dBFS at 172.3 MHz (1.59 V p-p analog input full scale) Ultrawideband satellite receiver Noise density Instrumentation −153.9 dBFS/Hz (1.59 V p-p analog input full scale) Oscilloscopes −155.6 dBFS/Hz (2.04 V p-p analog input full scale) Spectrum analyzers 0.95 V, 1.8 V, and 2.5 V supply operation Network analyzers No missing codes Integrated RF test solutions Internal ADC voltage reference Radars Flexible differential input voltage range Electronic support measures, electronic counter measures, 1.36 V p-p to 2.04 V p-p (1.59 V p-p typical) and electronic counter to counter measures 2 GHz usable analog input full power bandwidth High speed data acquisition systems Amplitude detect bits for efficient AGC implementation DOCSIS 3.0 CMTS upstream receive paths 4 integrated digital downconverters Hybrid fiber coaxial digital reverse path receivers 48-bit NCO Wideband digital predistortion Programmable decimation rates Differential clock input SPI control Integer clock divide by 2 and divide by 4 Flexible JESD204B lane configurations On-chip dithering to improve small signal linearity FUNCTIONAL BLOCK DIAGRAM AVDD1 AVDD2 AVDD3 AVDD1_SR DVDD DRVDD1 DRVDD2 SPIVDD (0.95V) (1.8V) (2.5V) (0.95V) (0.95V) (0.95V) (1.8V) (1.8V) E SIGNAL UX UX MONITOR ABL R SERDOUT0± M JESD204B 4 SERDOUT1± FAST DIGITAL DOWN- LINK DETECT BAR M CONVERTER BAR M SERDOUT2± AND RAM FILTE S S S S G Tx SERDOUT3± FIR OUTPUTS RO CRO CRO P VIN+ 14 ADC VIN– CORE BUFFER VREF SYNCINB± PDWN/STBY JESD204B CLOCK SYSREF± SUBCLASS 1 DISTRIBUTION CONTROL FD/GPIO1 CLK+ GPIO MUX SPI AND GPIO2 CONTROL REGISTERS CLK– ÷2 ÷4 AD9697
001
AGND SDIO SCLK CSB DRGND DGND
16253- Figure 1.
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Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION PRODUCT HIGHLIGHTS SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Differential Input Configurations Input Common Mode Analog Input Buffer Controls and SFDR Optimization Absolute Maximum Input Swing Dither VOLTAGE REFERENCE DC OFFSET CALIBRATION CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Input Clock Divider Input Clock Divider ½ Period Delay Adjust Clock Fine Delay and Superfine Delay Adjust Clock Coupling Considerations Clock Jitter Considerations POWER-DOWN/STANDBY MODE TEMPERATURE DIODE ADC OVERRANGE AND FAST DETECT ADC OVERRANGE FAST THRESHOLD DETECTION (FD) ADC APPLICATION MODES AND JESD204B Tx CONVERTER MAPPING PROGRAMMABLE FINITE IMPULSE RESPONSE (FIR) FILTERS SUPPORTED MODES PROGRAMMING INSTRUCTIONS DIGITAL DOWNCONVERTER (DDC) DDC I/Q OUTPUT SELECTION DDC GENERAL DESCRIPTION Frequency Translation Stage (Optional) Filtering Stage Gain Stage (Optional) Complex to Real Conversion Stage (Optional) DDC FREQUENCY TRANSLATION DDC Frequency Translation General Description Variable IF Mode 0 Hz IF (ZIF) Mode fS/4 Hz IF Mode Test Mode DDC NCO Description DDC NCO Programmable Modulus Mode DDC NCO Coherent Mode NCO FTW/POW/MAW/MAB Description NCO FTW/POW/MAW/MAB Programmable Modulus Mode NCO FTW/POW/MAW/MAB Coherent Mode NCO Channel Selection GPIO Level Control Mode GPIO Edge Control Mode Register Map Mode Setting Up the Multichannel NCO Feature NCO Synchronization NCO Multichip Synchronization NCO Multichip Synchronization at Startup NCO Multichip Synchronization During Normal Operation DDC Mixer Description DDC NCO + Mixer Loss and SFDR DDC DECIMATION FILTERS HB4 Filter Description HB3 Filter Description HB2 Filter Description HB1 Filter Description TB2 Filter Description TB1 Filter Description FB2 Filter Description DDC GAIN STAGE DDC COMPLEX TO REAL CONVERSION DDC MIXED DECIMATION SETTINGS DDC EXAMPLE CONFIGURATIONS SIGNAL MONITOR SPORT OVER JESD204B DIGITAL OUTPUTS INTRODUCTION TO THE JESD204B INTERFACE JESD204B OVERVIEW FUNCTIONAL OVERVIEW Transport Layer Data Link Layer Physical Layer JESD204B LINK ESTABLISHMENT Code Group Synchronization (CGS) Initial Lane Alignment Sequence (ILAS) User Data and Error Detection 8-Bit/10-Bit Encoder PHYSICAL LAYER (DRIVER) OUTPUTS Digital Outputs, Timing, and Controls De-Emphasis Phase-Locked Loop (PLL) SETTING UP THE AD9697 DIGITAL INTERFACE Example Setup 1—Full Bandwidth Mode Example Setup 2—ADC with DDC Option (Two ADCs Plus Two DDCs) DETERMINISTIC LATENCY SUBCLASS 0 OPERATION SUBCLASS 1 OPERATION Deterministic Latency Requirements Setting Deterministic Latency Registers MULTICHIP SYNCHRONIZATION NORMAL MODE TIMESTAMP MODE SYSREF± INPUT SYREF± Control Features SYSREF± SETUP/HOLD WINDOW MONITOR LATENCY END TO END TOTAL LATENCY EXAMPLE LATENCY CALCULATIONS LMFC REFERENCED LATENCY TEST MODES ADC TEST MODES JESD204B BLOCK TEST MODES Transport Layer Sample Test Mode Interface Test Modes Data Link Layer Test Modes SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open and Reserved Locations Default Values Logic Levels SPI Soft Reset MEMORY MAP REGISTERS APPLICATIONS INFORMATION POWER SUPPLY RECOMMENDATIONS LAYOUT GUIDELINES AVDD1_SR (PIN 57) AND AGND_SR (PIN 56 AND PIN 60) OUTLINE DIMENSIONS ORDERING GUIDE