Datasheet AD7790 (Analog Devices) - 5

Key Sheet AD7790 FREQUENTLY ASKED QUESTIONS What is the optional internal rail-to-rail buffer? Are there any ESD protection schemes that should be
The AD7790 has one differential analog input channel that is
considered for the AD7790?
• This converter is manufactured on a standard CMOS process; Connected to the on-chip buffer amplifier when the device is operated in buffered mode therefore, al standard practices and protection schemes that • apply to other CMOS devices also apply to this device. There Connected directly to the modulator when the device is operated in unbuffered mode are ESD protection diodes on al the inputs that protect the device from possible ESD damage due to handling and production. To In buffered mode, the input channel feeds into a high impedance determine the appropriate ESD precautions, refer to the AD7790 input stage of the buffer amplifier. Therefore, the input can data sheet for information about the absolute maximum ratings. tolerate significant source impedances and is tailored for direct
Is an antialiasing filter required?
connection to external resistive-type sensors, such as strain The analog input is sampled at 64 kHz. The digital filter does gauges or resistance temperature detectors (RTDs). not provide any rejection at this frequency or at frequencies that
What is 50 Hz and 60 Hz rejection?
are multiples of 64 kHz; an external antialiasing filter is required The mains power supply generates interference at 50 Hz or to provide rejection at these frequencies, with a simple RC filter 60 Hz, with the frequency varying from one country to another. being sufficient. Typical values for the filter are The AD7790 has the ability to simultaneously reject 50 Hz and • 1 kΩ resistor in series with each analog input 60 Hz signals at an ODR of 16.6 SPS. • 0.1 µF capacitor between the analog input pins
What MCLK divide options are available?
• 0.01 µF capacitor from each input pin to ground The AD7790 has a current consumption of 160 µA maximum when operated with the buffer enabled and with a 5 V power These typical values can be used only when the buffer is supply. The power can be reduced further by setting the CDIV1 enabled. When the buffer is disabled, smaller RC values are and CDIV0 bits in the filter register appropriately. required because larger values can cause gain errors. By setting these bits, the internal clock is divided by 2, 4, or 8 before
Can filtering be added to the reference pins?
being applied to the modulator and filter, resulting in a reduction of The reference input to the AD7790 is not buffered. Therefore, the output data rate and a reduction in the digital current. the filtering must be limited on the reference pins because large RC values can cause gain errors. Suitable capacitor values are
How do I interface with the part?
The part can be configured by using a 4-wire SPI interface; this • 2200 pF capacitor between the reference pins interface is also used as the data interface. The SPI interface allows • 220 pF capacitor from each pin to ground the user to read the status of the part and to change the setup. With these capacitor values, there can be some resistance in parallel with the reference pins. However, it must be limited to less than 100 Ω. Rev. 0 | Page 5 of 6 Document Outline General Description Features and Benefits Key Characteristics Fundamental Specifications Noise Operating the AD7790 Data Interface Data Modes Continuous Conversion Mode (Default) Continuous Read Mode Single Conversion Mode Typical Application Diagram Frequently Asked Questions Learn More and Start Designing Compatible Devices Package Diagram Getting Started