Datasheet AD7768-1 (Analog Devices) - 10

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AD7768-1 Data Sheet Parameter Test Conditions/Comments Min Typ Max Unit
Standby Mode SPI active, MCLK active, VCM off 780 μW SPI active, MCLK inactive, VCM off 125 μW Power-Down Mode Full power down, SPI control mode only 14 μW 1 The ODR ranges refer to the programmable decimation rates available on the AD7768-1 for a fixed MCLK rate of 16.384 MHz. Varying the MCLK rate allows the user a wider variation of ODR. 2 This specification is not production tested, but is supported by characterization data at initial product release. 3 The typical value (−20 μA) is measured when the analog input is close to either the AVDD1 or AVSS rail. The input current reduces as the common mode approaches the midpoint of the power supply rails: (AVDD1 − AVSS)/2. The analog input current scales with the MCLK frequency and the power mode (fast, median, and low power). 4 This specification is not production tested. It is supported by a combination of design simulation and test coverage on a limited number of units. 5 Alias rejection around frequencies related to the chop frequency may result in compound attenuation, which exceeds 105 dB. See the Antialiasing Filtering section describing front-end antialias protection for further detail. 6 VCM can typically source 10 mA, but it is recommended to source no more than 6 mA in normal operation.
3 V OPERATION
For low power mode only. AVDD1, AVDD2, and IOVDD = 3 V, DGND = 0 V, AVSS = 0 V, REF+ = 2.5V, and REF− = 0 V, MCLK = 16.384 MHz, analog input precharge buffers on, reference precharge on, the filter type is a low ripple FIR filter, chop frequency (fCHOP) = modulator frequency (fMOD)/32, and TA = TMIN to TMAX, unless otherwise noted.
Table 2. Parameter Test Conditions/Comments Min Typ Max Unit
ADC SPEED AND PERFORMANCE ODR1 Low power mode Low ripple FIR filter and sinc5 filter 1 32 kSPS Sinc3 0.0125 32 kSPS No Missing Codes2 Low ripple FIR, sinc5 decimation > 32 24 Bits DYNAMIC PERFORMANCE Low Power Mode Decimation by 32, 32 kHz ODR Dynamic Range Shorted inputs, sinc5 filter 106.9 dB Shorted inputs, low ripple FIR 100.9 104 dB SNR 1 kHz, −0.25 dBFS, sine input Low ripple FIR 102.5 dB SINAD 102.3 dB THD −125 −112 dB SFDR 1 kHz, −0.25 dBFS, sine input 120 dBc ACCURACY INL Endpoint method ±3 ppm of FSR Offset Error Low power mode ±40 ±175 μV Offset Error Drift2 Low power mode ±100 nV/°C Gain Error TA = 25°C ±30 ppm/FSR ANALOG INPUTS Differential Input Voltage VREF = REF+ − REF− VREF− VREF+ V Absolute AINx Voltage Analog input precharge buffers off, AVSS − 0.05 AVDD1 + 0.05 V absolute voltage on AIN+ or AIN− Analog Input Current Input Current Unbuffered Differential component ±53 μA/V Common-mode component ±17 μA/V Input Current3 Precharge buffers on, external CMOS MCLK −20 μA Rev. A | Page 10 of 80 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS 3 V OPERATION TIMING SPECIFICATIONS 1.8 V TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CLOCKING, SAMPLING TREE, AND POWER SCALING Power vs. Noise Performance Optimization Example of Power vs. Noise Performance Optimization Configuration A Configuration B NOISE PERFORMANCE AND RESOLUTION CORE CONVERTER ADC Core and Signal Chain Analog Inputs and Precharge Buffering VCM Output Reference Input and Buffering CLOCKING AND CLOCK SELECTION CLKSEL Pin Using the Internal Oscillator DIGITAL FILTERING Sinc5 Filter Sinc3 Filter Programming for 50 Hz, 60 Hz, and 50 Hz and 60 Hz Rejection Low Ripple FIR Filter DECIMATION RATE CONTROL ANTIALIASING FILTERING Modulator Saturation Point Modulator Unprotected Zones Modulator Chopping Frequency GETTING STARTED Method of Configuration—PINB Control Mode or SPI Control Mode Digital Filter Type and Decimation Power Mode POWER SUPPLIES Single-Supply Mode Recommended Power Supply Configuration DEVICE CONFIGURATION METHOD PINB Configuration SPI Control PIN CONTROL MODE OVERVIEW Power Mode Data Output Format Diagnostics and Status Bits Daisy-Chaining—PINB Control Mode Only SPI CONTROL OVERVIEW SPI CONTROL MODE MCLK Source and MCLK Division Power-Down Mode Standby Mode SPI Synchronization Offset Calibration Gain Calibration Reset over SPI Control Interface Resume from Shutdown GPIO and STARTB Functions SPI Mode Diagnostic Features Reference Detection Clock Qualification CRC on SPI Transaction Flags for Detection of Illegal Register Write CRC Checks POR Monitor MCLK Counter Product Identification (ID) Number DIGITAL INTERFACE SPI Reading and Writing SPI Control Interface Error Handling CRC Check on Serial Interface Conversion Read Modes Single-Conversion Read Mode Continuous Read Mode Exiting Continuous Read Mode DATA CONVERSION MODES Continuous Conversion Mode One Shot Conversion Mode Single-Conversion Mode Duty Cycled Conversion Mode SYNCHRONIZATION OF MULTIPLE AD7768-1 DEVICES ADDITIONAL FUNCTIONALITY OF THE AD7768-1 Reset Status Header Diagnostics APPLICATIONS INFORMATION ANALOG INPUT RECOMMENDATIONS Recommended Driver Amplifiers ANTIALIASING FILTER DESIGN CONSIDERATIONS RECOMMENDED INTERFACE Initializing the Recommended Interface Recommended Interface for Reading Data Resynchronization of the Recommended Interface PROGRAMMABLE DIGITAL FILTER Filter Coefficients Upload Sequence Example Filter Upload Filter Upload Verification ELECTROMAGNETIC COMPATIBILITY (EMC) TESTING Radiated Immunity Radiated Emissions Electrical Fast Transients (EFTs) AD7768-1 SUBSYSTEM LAYOUT REGISTER SUMMARY REGISTER DETAILS COMPONENT TYPE REGISTER UNIQUE PRODUCT ID REGISTERS DEVICE GRADE AND REVISION REGISTER USER SCRATCHPAD REGISTER DEVICE VENDOR ID REGISTERS INTERFACE FORMAT CONTROL REGISTER POWER AND CLOCK CONTROL REGISTER ANALOG BUFFER CONTROL REGISTER VCM CONTROL REGISTER CONVERSION SOURCE SELECT AND MODE CONTROL REGISTER DIGITAL FILTER AND DECIMATION CONTROL REGISTER SINC3 DECIMATION RATE (MSB REGISTER) SINC3 DECIMATION RATE (LSB REGISTER) PERIODIC CONVERSION RATE CONTROL REGISTER SYNCHRONIZATION MODES AND RESET TRIGGERING REGISTER GPIO PORT CONTROL REGISTER GPIO OUTPUT CONTROL REGISTER GPIO INPUT READ REGISTER OFFSET CALIBRATION MSB REGISTER OFFSET CALIBRATION MID REGISTER OFFSET CALIBRATION LSB REGISTER GAIN CALIBRATION MSB REGISTER GAIN CALIBRATION MID REGISTER GAIN CALIBRATION LSB REGISTER SPI INTERFACE DIAGNOSTIC CONTROL REGISTER ADC DIAGNOSTIC FEATURE CONTROL REGISTER DIGITAL DIAGNOSTIC FEATURE CONTROL REGISTER CONVERSION RESULT REGISTER DEVICE ERROR FLAGS MASTER REGISTER SPI INTERFACE ERROR REGISTER ADC DIAGNOSTICS OUTPUT REGISTER DIGITAL DIAGNOSTICS OUTPUT REGISTER MCLK DIAGNOSTIC OUTPUT REGISTER COEFFICIENT CONTROL REGISTER COEFFICIENT DATA REGISTER ACCESS KEY REGISTER OUTLINE DIMENSIONS ORDERING GUIDE