Datasheet AD7768-1 (Analog Devices) - 8

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AD7768-1 Data Sheet Parameter Test Conditions/Comments Min Typ Max Unit
CLOCK MCLK External Clock 0.6 16.384 17 MHz Internal Clock 16.384 MHz Duty Cycle2 16.384 MHz MCLK 25:75 50:50 75:25 % Crystal Frequency 8 16 17 MHz Start-Up Time Clock output valid 2 ms ADC RESET ADC Start-Up Time Reset rising edge to first DRDY, PIN mode, 100 µs After Reset decimate by 8 Reset Low Pulse Width 0.0001 100 ms LOGIC INPUTS Input Voltage High, VINH 1.7 V ≤ IOVDD ≤ 1.9 V 0.65 × IOVDD V 2.2 V ≤ IOVDD ≤ 3.6 V 0.65 × IOVDD V Low, VINL 1.7 V ≤ IOVDD ≤ 1.9 V 0.35 × IOVDD V 2.2 V ≤ IOVDD ≤ 3.6 V 0.7 V Hysteresis2 2.2 V ≤ IOVDD ≤ 3.6 V 0.08 0.25 V 1.7 V ≤ IOVDD ≤ 1.9 V 0.04 0.2 V Leakage Current Excluding RESET pin −10 +0.05 +10 µA RESET pin pull-up resistor 1 kΩ LOGIC OUTPUTS Output Voltage2 High, VOH 2.2 V ≤ IOVDD < 3.6 V, source current 0.8 × IOVDD V (ISOURCE) = 500 µA, LV_BOOST off 1.7 V ≤ IOVDD ≤ 1.9 V, ISOURCE = 200 µA, 0.8 × IOVDD V LV_BOOST on Low, VOL 2.2 V ≤ IOVDD < 3.6 V, sink current (ISINK) = 0.4 V 1 mA, LV_BOOST off 1.7 V ≤ IOVDD ≤ 1.9 V, 0.4 V ISINK = 400 µA, LV_BOOST on Leakage Current Floating state −10 +10 µA Output Capacitance Floating state 10 pF VCM OUTPUT Default setting AVDD1 − V AVSS/2 VCM Noise4 VCM = (AVDD1 – AVSS)/2, from 10 µV rms simulation, 1 kHz bandwidth limited VCM = 2.5 V, from simulation, 1 kHz 65 µV rms bandwidth limited Short-Circuit Current6 10 mA Load Regulation 1 mV/mA POWER REQUIREMENTS Power supply voltages AVDD1 − AVSS Al power modes 4.5 5.0 5.5 V AVDD1 − AVSS Low power mode only 3 5.5 V AVDD2 − AVSS 2 2.0 to 5.0 5.5 V AVSS − DGND −2.75 0 V IOVDD − DGND 1.7 1.8 to 3.3 3.6 V Rev. A | Page 8 of 80 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS 3 V OPERATION TIMING SPECIFICATIONS 1.8 V TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CLOCKING, SAMPLING TREE, AND POWER SCALING Power vs. Noise Performance Optimization Example of Power vs. Noise Performance Optimization Configuration A Configuration B NOISE PERFORMANCE AND RESOLUTION CORE CONVERTER ADC Core and Signal Chain Analog Inputs and Precharge Buffering VCM Output Reference Input and Buffering CLOCKING AND CLOCK SELECTION CLKSEL Pin Using the Internal Oscillator DIGITAL FILTERING Sinc5 Filter Sinc3 Filter Programming for 50 Hz, 60 Hz, and 50 Hz and 60 Hz Rejection Low Ripple FIR Filter DECIMATION RATE CONTROL ANTIALIASING FILTERING Modulator Saturation Point Modulator Unprotected Zones Modulator Chopping Frequency GETTING STARTED Method of Configuration—PINB Control Mode or SPI Control Mode Digital Filter Type and Decimation Power Mode POWER SUPPLIES Single-Supply Mode Recommended Power Supply Configuration DEVICE CONFIGURATION METHOD PINB Configuration SPI Control PIN CONTROL MODE OVERVIEW Power Mode Data Output Format Diagnostics and Status Bits Daisy-Chaining—PINB Control Mode Only SPI CONTROL OVERVIEW SPI CONTROL MODE MCLK Source and MCLK Division Power-Down Mode Standby Mode SPI Synchronization Offset Calibration Gain Calibration Reset over SPI Control Interface Resume from Shutdown GPIO and STARTB Functions SPI Mode Diagnostic Features Reference Detection Clock Qualification CRC on SPI Transaction Flags for Detection of Illegal Register Write CRC Checks POR Monitor MCLK Counter Product Identification (ID) Number DIGITAL INTERFACE SPI Reading and Writing SPI Control Interface Error Handling CRC Check on Serial Interface Conversion Read Modes Single-Conversion Read Mode Continuous Read Mode Exiting Continuous Read Mode DATA CONVERSION MODES Continuous Conversion Mode One Shot Conversion Mode Single-Conversion Mode Duty Cycled Conversion Mode SYNCHRONIZATION OF MULTIPLE AD7768-1 DEVICES ADDITIONAL FUNCTIONALITY OF THE AD7768-1 Reset Status Header Diagnostics APPLICATIONS INFORMATION ANALOG INPUT RECOMMENDATIONS Recommended Driver Amplifiers ANTIALIASING FILTER DESIGN CONSIDERATIONS RECOMMENDED INTERFACE Initializing the Recommended Interface Recommended Interface for Reading Data Resynchronization of the Recommended Interface PROGRAMMABLE DIGITAL FILTER Filter Coefficients Upload Sequence Example Filter Upload Filter Upload Verification ELECTROMAGNETIC COMPATIBILITY (EMC) TESTING Radiated Immunity Radiated Emissions Electrical Fast Transients (EFTs) AD7768-1 SUBSYSTEM LAYOUT REGISTER SUMMARY REGISTER DETAILS COMPONENT TYPE REGISTER UNIQUE PRODUCT ID REGISTERS DEVICE GRADE AND REVISION REGISTER USER SCRATCHPAD REGISTER DEVICE VENDOR ID REGISTERS INTERFACE FORMAT CONTROL REGISTER POWER AND CLOCK CONTROL REGISTER ANALOG BUFFER CONTROL REGISTER VCM CONTROL REGISTER CONVERSION SOURCE SELECT AND MODE CONTROL REGISTER DIGITAL FILTER AND DECIMATION CONTROL REGISTER SINC3 DECIMATION RATE (MSB REGISTER) SINC3 DECIMATION RATE (LSB REGISTER) PERIODIC CONVERSION RATE CONTROL REGISTER SYNCHRONIZATION MODES AND RESET TRIGGERING REGISTER GPIO PORT CONTROL REGISTER GPIO OUTPUT CONTROL REGISTER GPIO INPUT READ REGISTER OFFSET CALIBRATION MSB REGISTER OFFSET CALIBRATION MID REGISTER OFFSET CALIBRATION LSB REGISTER GAIN CALIBRATION MSB REGISTER GAIN CALIBRATION MID REGISTER GAIN CALIBRATION LSB REGISTER SPI INTERFACE DIAGNOSTIC CONTROL REGISTER ADC DIAGNOSTIC FEATURE CONTROL REGISTER DIGITAL DIAGNOSTIC FEATURE CONTROL REGISTER CONVERSION RESULT REGISTER DEVICE ERROR FLAGS MASTER REGISTER SPI INTERFACE ERROR REGISTER ADC DIAGNOSTICS OUTPUT REGISTER DIGITAL DIAGNOSTICS OUTPUT REGISTER MCLK DIAGNOSTIC OUTPUT REGISTER COEFFICIENT CONTROL REGISTER COEFFICIENT DATA REGISTER ACCESS KEY REGISTER OUTLINE DIMENSIONS ORDERING GUIDE