Datasheet AD4110-1 (Analog Devices) - 10

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AD4110-1 Data Sheet ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted. Stresses at or above those listed under Absolute Maximum
Table 3.
Ratings may cause permanent damage to the product. This is a
Parameter Rating
stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational Any HV Pin to VSS1, 2 −0.3 V to +60 V section of this specification is not implied. Operation beyond VDD to VSS3 −0.3 V to +50 V the maximum operating conditions for extended periods may AIN(+) to AIN(−)4 ±50 V affect product reliability. AVDD5 to AGND, DGND3, 5 −0.3 V to +6.5 V IOVDD to AGND, DGND3, 5 −0.3 V to +6.5 V
THERMAL RESISTANCE
AGND to DGND5 −0.3 V to +0.3 V Thermal performance is directly linked to printed circuit board AGND to VSS AGND ≥ VSS − 0.3 V (PCB) design and operating environment. Close attention to AVDD5 to VDD AVDD5 ≤ VDD + 0.3 V PCB thermal design is required. REFIN(+), REFIN(−), AIN1(LV), −0.3 V to AVDD5 + 0.3 V AIN2(LV), AINCOM(LV) to AGND
Table 4. Thermal Resistance
Digital Inputs and Outputs to DGND −0.3 V to IOVDD + 0.3 V
Package Type θJA Unit
Operating Temperature Range −40°C to +105°C CP-40-151 35 °C/W Storage Temperature Range −65°C to +150°C Maximum Junction Temperature 150°C 1 θJA is specified for a device soldered on a JEDEC 4-layer test board for surface-mount packages with 16 thermal vias. The values listed in Table 4 Electrostatic Discharge (ESD), 700 V are based on simulated data. Human Body Model Field Induced Charge Device 1250 V
ESD CAUTION
Model (FICDM) Reflow Soldering (Pb-Free) JEDEC J-STD-020 Peak Temperature 260°C Time at Peak Temperature 10 sec to 40 sec 1 HV pins are AIN(+), AIN(−), RTD, EXRS, and EXRF. 2 Applying a voltage to an HV pin that is more negative than the potential of the system negative power supply can only be accomplished by connecting an external diode from the VSS pin to the system negative power supply (see Figure 29). 3 Pins with the same name must be shorted together. 4 Using an input RC low-pass filter with R = 10 Ω, 0.5 W and C = 47 nF, 50 V. 5 It is recommended to short AGND and DGND pins together as close to the device as possible. Rev. 0 | Page 10 of 74 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION POWER SUPPLY SEQUENCE PROTECTION DIODE ANALOG INPUT PULL-UP/PULL-DOWN CURRENTS ANTIALIASING FILTER RTD EXCITATION CURRENTS FIELD POWER SUPPLY MODE NO POWER SUPPLY MODE BIAS VOLTAGE GENERATOR PGA CALIBRATION REGISTERS SERIAL INTERFACE CLOCK ADC ADC FILTER REGISTERS ADC GAIN AND OFFSET REGISTERS NOISE PERFORMANCE AND RESOLUTION MODES OF OPERATION DEFAULT MODE OF OPERATION ON POWER-UP CHANGING THE DEFAULT MODE OF OPERATION FOR FUTURE POWER-UP CYCLES POWER SUPPLY REQUIREMENTS SYSTEM CLOCK REQUIREMENTS BIPOLAR AND UNIPOLAR OUTPUT AUXILIARY LOW VOLTAGE INPUTS DIGITAL FILTER CONTINUOUS CONVERSION MODE INPUT AUTO SEQUENCING SINGLE CONVERSION MODE ADC CONVERSION DELAY BIAS VOLTAGE GENERATOR ANTIALIASING FILTER CIRCUIT CURRENT MODE Transimpedance Gain Using an External Sense Resistor VOLTAGE AND THERMOCOUPLE MODE Input Scaling for Voltage Mode Thermocouple Inputs RTD MODE Generating RTD Currents with an External Resistor Excitation Currents RTD Initial Drift 4-Wire RTD 3-Wire RTD 2-Wire RTD Alternative 3-Wire Configuration FIELD POWER SUPPLY MODE Overvoltage Protection NO POWER SUPPLY MODE Voltage Mode Current Mode System Redundancy GAIN CALIBRATION DATA REGISTER GAIN CALIBRATION IN VOLTAGE MODE GAIN CALIBRATION IN CURRENT MODE SCALING FACTOR AUTOCALIBRATION MODES APPLICATION EXAMPLES Example 1 Example 2 DIAGNOSTICS AND PROTECTION DIAGNOSTIC FLAGS ERROR PIN OVERTEMPERATURE DETECTION AND THERMAL SHUTDOWN OVERVOLTAGE AND UNDERVOLTAGE DETECTION OVERVOLTAGE PROTECTION DIAGNOSING OVERVOLTAGE AND UNDERVOLTAGE CONDITIONS OPEN WIRE DETECTION DIAGNOSTICS FOR RTD MEASUREMENTS AND RTD FLAGS NOISE, SETTLING TIME, AND DIGITAL FILTERING DIGITAL FILTER SINC5 + SINC1 FILTER SINC3 FILTER ENHANCED 50 HZ AND 60 HZ REJECTION FILTERS RTD MODE NOISE PERFORMANCE SERIAL PERIPHERAL INTERFACE RESETTING THE AD4110-1 SPI COMMAND TO COMMUNICATIONS REGISTER DOUT/ PIN WRITE OPERATION READ OPERATION MULTIPLE DEVICES ON THE SPI BUS CRC CHECKSUM CRC CHECKSUM METHODS Polynomial Calculation Polynomial CRC Calculation of a 24-Bit Word: 0x654321 (Eight Command Bits and 16-Bit Data) XOR Calculation REGISTER DETAILS AFE REGISTER MAP AFE REGISTER DESCRIPTIONS AFE_TOP_STATUS Register AFE_CNTRL1 Register AFE_CLK_CTRL Register AFE_CNTRL2 Register PGA_RTD_CTRL Register AFE_ERR_DISABLE Register AFE_DETAIL_STATUS Register AFE_CAL_DATA Register AFE_RSENSE_DATA Register NO_PWR_DEFAULT_SEL Register NO_PWR_DEFAULT_STATUS Register ADC REGISTER MAP ADC REGISTER DESCRIPTIONS ADC_STATUS Register ADC_MODE Register ADC_INTERFACE Register ADC_CONFIG Register Data Register Filter Register ADC_GPIO_CONFIG Register ID Register ADC_OFFSET0 Register ADC_OFFSET1 Register ADC_OFFSET2 Register ADC_OFFSET3 Register ADC_GAIN0 Register ADC_GAIN1 Register ADC_GAIN2 Register ADC_GAIN3 Register OUTLINE DIMENSIONS ORDERING GUIDE