Datasheet AD4110-1 (Analog Devices) - 9

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Data Sheet AD4110-1 TIMING SPECIFICATIONS
IOVDD = 2 V to 5.5 V, AGND = DGND = 0 V, CLOAD = 20 pF, TA = −40°C to +105°C, unless otherwise noted.
Table 2. Parameter Limit at TMIN, TMAX Unit Description1, 2
t3 50 ns min SCLK high pulse width t4 50 ns min SCLK low pulse width READ OPERATION t1 0 ns min CS falling edge to DOUT/RDY active time 15 ns max IOVDD = 4.5 V to 5.5 V 20 ns max IOVDD = 3.0 V to 3.6 V 40 ns max IOVDD = 2.0 V t 3 2 0 ns min SCLK active edge to data valid delay4 15 ns max IOVDD = 4.5 V to 5.5 V 20 ns max IOVDD = 3.0 V to 3.6 V 40 ns max IOVDD = 2.0 V t 5 5 20 ns max Bus relinquish time after CS inactive edge t6 0 ns min SCLK inactive edge to CS inactive edge WRITE OPERATION t8 0 ns min CS falling edge to SCLK active edge setup time4 t9 8 ns min Data valid to SCLK edge setup time t10 8 ns min Data valid to SCLK edge hold time t11 10 ns min CS rising edge to SCLK edge hold time 1 Sample tested during initial release to ensure compliance. 2 See Figure 2 and Figure 3. 3 t2 is the time required for the output to cross the VOL or VOH limit. 4 The SCLK active edge is the falling edge of SCLK. 5 DOUT/RDY returns high after a read of the data register. In single conversion mode and continuous conversion mode, the same data can be read again, if required, while DOUT/RDY is high, although care must be taken to ensure that subsequent reads do not occur close to the next output update.
Timing Diagrams CS (I) t6 t1 t5 DOUT/RDY (O) MSB LSB t2 t3 SCLK (I) t4
002
I = INPUT, O = OUTPUT
16269- Figure 2. Data Read Timing Diagram
CS (I) t t 8 11 SCLK (I) t9 t10 DIN (I) MSB LSB
003
I = INPUT, O = OUTPUT
16269- Figure 3. Data Write Timing Diagram Rev. 0 | Page 9 of 74 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION POWER SUPPLY SEQUENCE PROTECTION DIODE ANALOG INPUT PULL-UP/PULL-DOWN CURRENTS ANTIALIASING FILTER RTD EXCITATION CURRENTS FIELD POWER SUPPLY MODE NO POWER SUPPLY MODE BIAS VOLTAGE GENERATOR PGA CALIBRATION REGISTERS SERIAL INTERFACE CLOCK ADC ADC FILTER REGISTERS ADC GAIN AND OFFSET REGISTERS NOISE PERFORMANCE AND RESOLUTION MODES OF OPERATION DEFAULT MODE OF OPERATION ON POWER-UP CHANGING THE DEFAULT MODE OF OPERATION FOR FUTURE POWER-UP CYCLES POWER SUPPLY REQUIREMENTS SYSTEM CLOCK REQUIREMENTS BIPOLAR AND UNIPOLAR OUTPUT AUXILIARY LOW VOLTAGE INPUTS DIGITAL FILTER CONTINUOUS CONVERSION MODE INPUT AUTO SEQUENCING SINGLE CONVERSION MODE ADC CONVERSION DELAY BIAS VOLTAGE GENERATOR ANTIALIASING FILTER CIRCUIT CURRENT MODE Transimpedance Gain Using an External Sense Resistor VOLTAGE AND THERMOCOUPLE MODE Input Scaling for Voltage Mode Thermocouple Inputs RTD MODE Generating RTD Currents with an External Resistor Excitation Currents RTD Initial Drift 4-Wire RTD 3-Wire RTD 2-Wire RTD Alternative 3-Wire Configuration FIELD POWER SUPPLY MODE Overvoltage Protection NO POWER SUPPLY MODE Voltage Mode Current Mode System Redundancy GAIN CALIBRATION DATA REGISTER GAIN CALIBRATION IN VOLTAGE MODE GAIN CALIBRATION IN CURRENT MODE SCALING FACTOR AUTOCALIBRATION MODES APPLICATION EXAMPLES Example 1 Example 2 DIAGNOSTICS AND PROTECTION DIAGNOSTIC FLAGS ERROR PIN OVERTEMPERATURE DETECTION AND THERMAL SHUTDOWN OVERVOLTAGE AND UNDERVOLTAGE DETECTION OVERVOLTAGE PROTECTION DIAGNOSING OVERVOLTAGE AND UNDERVOLTAGE CONDITIONS OPEN WIRE DETECTION DIAGNOSTICS FOR RTD MEASUREMENTS AND RTD FLAGS NOISE, SETTLING TIME, AND DIGITAL FILTERING DIGITAL FILTER SINC5 + SINC1 FILTER SINC3 FILTER ENHANCED 50 HZ AND 60 HZ REJECTION FILTERS RTD MODE NOISE PERFORMANCE SERIAL PERIPHERAL INTERFACE RESETTING THE AD4110-1 SPI COMMAND TO COMMUNICATIONS REGISTER DOUT/ PIN WRITE OPERATION READ OPERATION MULTIPLE DEVICES ON THE SPI BUS CRC CHECKSUM CRC CHECKSUM METHODS Polynomial Calculation Polynomial CRC Calculation of a 24-Bit Word: 0x654321 (Eight Command Bits and 16-Bit Data) XOR Calculation REGISTER DETAILS AFE REGISTER MAP AFE REGISTER DESCRIPTIONS AFE_TOP_STATUS Register AFE_CNTRL1 Register AFE_CLK_CTRL Register AFE_CNTRL2 Register PGA_RTD_CTRL Register AFE_ERR_DISABLE Register AFE_DETAIL_STATUS Register AFE_CAL_DATA Register AFE_RSENSE_DATA Register NO_PWR_DEFAULT_SEL Register NO_PWR_DEFAULT_STATUS Register ADC REGISTER MAP ADC REGISTER DESCRIPTIONS ADC_STATUS Register ADC_MODE Register ADC_INTERFACE Register ADC_CONFIG Register Data Register Filter Register ADC_GPIO_CONFIG Register ID Register ADC_OFFSET0 Register ADC_OFFSET1 Register ADC_OFFSET2 Register ADC_OFFSET3 Register ADC_GAIN0 Register ADC_GAIN1 Register ADC_GAIN2 Register ADC_GAIN3 Register OUTLINE DIMENSIONS ORDERING GUIDE