Datasheet ADRF6520 (Analog Devices) - 3

Data Sheet ADRF6520 SPECIFICATIONS
VPS, VPSD = 3.3 V, TA = 25°C, ZLOAD = 100 Ω.
Table 1. Parameter Test Conditions/Comments Min Typ Max Unit
FREQUENCY RESPONSE, FILTER BYPASS MODE ±1 dB Gain Flatness Bandwidth I or Q channel 1.25 GHz FREQUENCY RESPONSE Low-Pass Corner Frequency, fC Corner Frequencies Four-pole Butterworth filter, −1 dB bandwidth 36 MHz 72 MHz 144 MHz 288 MHz 432 MHz 576 MHz 720 MHz Corner Frequency Absolute Accuracy Over operating temperature range ±8 % fC Corner Frequency Matching Channel A and Channel B at same gain and bandwidth ±0.5 % fC settings Pass-Band Flatness Defined as difference between value at 100 kHz and fC Corner Frequency = 72 MHz 0.2 dB Bypass Mode 1.5 dB Gain Matching Channel A and Channel B at same gain and bandwidth ±0.1 dB settings; 1 kHz to fC Group Delay Variation From midband to peak Corner Frequency = 36 MHz 4 ns Corner Frequency = 144 MHz 0.8 ns Corner Frequency = 720 MHz 0.25 ns Bypass Mode 0.15 ns Group Delay Matching At fC/2; Channel A and Channel B at same gain Corner Frequency = 36 MHz ±60 ps Corner Frequency = 144 MHz ±50 ps Corner Frequency = 720 MHz ±15 ps Bypass Mode ±10 ps Stop-Band Rejection Gain = 53 dB Relative to Pass Band 2 × fC −20 dB 5 × fC −50 dB 10 × fC −80 dB INPUT STAGE INP1, INM1, INP2, INM2 Maximum Input Swing At minimum gain, VGN1 = 0 V 4.0 V p-p Differential Input Impedance 100 Ω Input Common Mode AC coupling recommended 1.375 V RMS DETECTOR VRMS, CFLT1, CFLT2 Output Scaling Relative to the summation of the differential voltage at 1 V/V rms filter input of both channels Output Current Source available 3 mA Output Load To reach full scale 1 kΩ GAIN CONTROL VGN1, VGN2 Gain Range Maximum gain 53 dB Minimum gain −7 Attenuation Range Each attenuator; VGN1 or VGN2 = 1.5 V −30 0 dB Each attenuator; VGN1 or VGN2 = 0 V 30 dB Gain Slope 30 mV/dB Gain Error VGAIN from 500 mV to 1000 mV 0.2 dB Rev. 0 | Page 3 of 29 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION INPUT VGAs RMS DETECTOR PROGRAMMABLE FILTERS Bypassing the Filters VARIABLE GAIN AMPLIFIERS OUTPUT BUFFERS/ADC DRIVERS DC OFFSET COMPENSATION LOOP PROGRAMMING THE ADRF6520 NOISE CHARACTERISTICS DISTORTION CHARACTERISTICS MAXIMIZING THE DYNAMIC RANGE KEY PARAMETERS FOR QUADRATURE-BASED RECEIVERS SPI REGISTER AND TIMING REGISTER READ/WRITE TIMING Write Cycle Read Cycle APPLICATIONS INFORMATION BASIC CONNECTIONS SUPPLY DECOUPLING INPUT SIGNAL PATH OUTPUT SIGNAL PATH DC OFFSET COMPENSATION LOOP ENABLED SERIAL PORT CONNECTIONS ENABLE/DISABLE FUNCTION GAIN PIN DECOUPLING RMS DETECTOR CONNECTIONS VGA2 GAIN STEP RESPONSE LINEAR OPERATION OF THE ADRF6520 EVALUATION BOARD OUTLINE DIMENSIONS ORDERING GUIDE