Datasheet AD7490-EP (Analog Devices) - 5
| Hersteller | Analog Devices |
| Beschreibung | 16-Channel, 1MSPS, 12-Bit ADC with Sequencer in 28-Lead TSSOP |
| Seiten / Seite | 12 / 5 — Enhanced Product. AD7490-EP. TIMING SPECIFICATIONS. Table 2. Timing … |
| Revision | B |
| Dateiformat / Größe | PDF / 406 Kb |
| Dokumentensprache | Englisch |
Enhanced Product. AD7490-EP. TIMING SPECIFICATIONS. Table 2. Timing Specifications1 Parameter Limit at TMIN, TMAX. Unit
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Enhanced Product AD7490-EP TIMING SPECIFICATIONS
VDD = 4.75 V to 5.25 V, VDRIVE ≤ VDD, REFIN = 2.5 V; TA = TMIN to TMAX, unless otherwise noted.
Table 2. Timing Specifications1 Parameter Limit at TMIN, TMAX Unit Description
f 2 SCLK 10 kHz min 20 MHz max tCONVERT 16 × tSCLK tQUIET 50 ns min Minimum quiet time required between bus relinquish and start of next conversion t2 10 ns min CS to SCLK setup time t 3 3 14 ns max Delay from CS until DOUT three-state disabled t3b4 20 ns max Delay from CS to DOUT valid t 3 4 40 ns max Data access time after SCLK falling edge t5 0.4 × tSCLK ns min SCLK low pulse width t6 0.4 × tSCLK ns min SCLK high pulse width t7 15 ns min SCLK to DOUT valid hold time t 5 8 15/50 ns min/max SCLK falling edge to DOUT high impedance t9 20 ns min DIN setup time prior to SCLK falling edge t10 5 ns min DIN hold time after SCLK falling edge t11 20 ns min 16th SCLK falling edge to CS high t12 1 µs max Power-up time from full power-down/auto shutdown/auto standby modes 1 Guaranteed by characterization. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V (see Figure 2). 2 The mark/space ratio for the SCLK input is 40/60 to 60/40. 3 Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.4 V or 0.7 VDRIVE . 4 t3b represents a worst-case figure for having ADD3 available on the DOUT line, that is, if the AD7490-EP goes back into three-state at the end of a conversion and some other device takes control of the bus between conversions, the user has to wait a maximum time of t3b before having ADD3 valid on the DOUT line. If the DOUT line is weakly driven to ADD3 between conversions, the user typically has to wait 12 ns at 5 V after the CS falling edge before seeing ADD3 valid on DOUT. 5 t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated back to remove the effects of charging or discharging the 25 pF capacitor. This means that the time, t8, quoted in the timing characteristics, is the true bus relinquish time of the part and is independent of the bus loading.
200µA IOL TO OUTPUT 1.6V PIN CL 25pF
002
200µA IOH
08936- Figure 2. Load Circuit for Digital Output Timing Specifications Rev. B | Page 5 of 12 Document Outline Features Enhanced Product Features Functional Block Diagram General Description Product Highlights Revision History Specifications Timing Specifications Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Outline Dimensions Ordering Guide
Enhanced Product AD7490-EP TIMING SPECIFICATIONS
VDD = 4.75 V to 5.25 V, VDRIVE ≤ VDD, REFIN = 2.5 V; TA = TMIN to TMAX, unless otherwise noted.
Table 2. Timing Specifications1 Parameter Limit at TMIN, TMAX Unit Description
f 2 SCLK 10 kHz min 20 MHz max tCONVERT 16 × tSCLK tQUIET 50 ns min Minimum quiet time required between bus relinquish and start of next conversion t2 10 ns min CS to SCLK setup time t 3 3 14 ns max Delay from CS until DOUT three-state disabled t3b4 20 ns max Delay from CS to DOUT valid t 3 4 40 ns max Data access time after SCLK falling edge t5 0.4 × tSCLK ns min SCLK low pulse width t6 0.4 × tSCLK ns min SCLK high pulse width t7 15 ns min SCLK to DOUT valid hold time t 5 8 15/50 ns min/max SCLK falling edge to DOUT high impedance t9 20 ns min DIN setup time prior to SCLK falling edge t10 5 ns min DIN hold time after SCLK falling edge t11 20 ns min 16th SCLK falling edge to CS high t12 1 µs max Power-up time from full power-down/auto shutdown/auto standby modes 1 Guaranteed by characterization. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V (see Figure 2). 2 The mark/space ratio for the SCLK input is 40/60 to 60/40. 3 Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.4 V or 0.7 VDRIVE . 4 t3b represents a worst-case figure for having ADD3 available on the DOUT line, that is, if the AD7490-EP goes back into three-state at the end of a conversion and some other device takes control of the bus between conversions, the user has to wait a maximum time of t3b before having ADD3 valid on the DOUT line. If the DOUT line is weakly driven to ADD3 between conversions, the user typically has to wait 12 ns at 5 V after the CS falling edge before seeing ADD3 valid on DOUT. 5 t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated back to remove the effects of charging or discharging the 25 pF capacitor. This means that the time, t8, quoted in the timing characteristics, is the true bus relinquish time of the part and is independent of the bus loading.
200µA IOL TO OUTPUT 1.6V PIN CL 25pF
002
200µA IOH
08936- Figure 2. Load Circuit for Digital Output Timing Specifications Rev. B | Page 5 of 12 Document Outline Features Enhanced Product Features Functional Block Diagram General Description Product Highlights Revision History Specifications Timing Specifications Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Outline Dimensions Ordering Guide