Datasheet AD7490-EP (Analog Devices)

16-Channel, 1 MSPS, 12-Bit ADC with Sequencer in 28-Lead TSSOP Enhanced Product AD7490-EP FEATURES FUNCTIONAL BLOCK DIAGRAM Fast throughput rate: 1 MSPS VDD Specified for VDD of 4.75 V to 5.25 V AD7490-EP Low power at maximum throughput rates REFIN 12.5 mW maximum at 1 MSPS with 5 V supplies 12-BIT 16 (single-ended) inputs with sequencer V SUCCESSIVE IN0 T/H APPROXIMATION Wide input bandwidth ADC 69.5 dB SNR at 50 kHz input frequency INPUT MUX Flexible power/serial clock speed management No pipeline delays VIN15 High speed serial interface, SPI/QSPI™/MICROWIRE™/ SCLK DSP compatible CONTROL DOUT Full shutdown mode: 0.5 µA maximum SEQUENCER LOGIC DIN 28-lead TSSOP package CS V ENHANCED PRODUCT FEATURES DRIVE
001
AGND Supports defense and aerospace applications (AQEC standard)
08936-
Military temperature range (−55°C to +125°C)
Figure 1.
Controlled manufacturing baseline One assembly/test site One fabrication site Product change notification Qualification data available on request GENERAL DESCRIPTION
is determined by the SCLK frequency because this is also used as The AD7490-EP is a 12-bit high speed, low power, 16-channel, the master clock to control the conversion. successive approximation ADC. The part operates from a single The AD7490-EP is available in a 28-lead TSSOP package. 4.75 V to 5.25 V power supply and features throughput rates up to Ful details about this enhanced product are available in the 1 MSPS. The part contains a low noise, wide bandwidth track-and- AD7490 data sheet, which should be consulted in conjunction with hold amplifier that can handle input frequencies in excess of this data sheet. 1 MHz.
PRODUCT HIGHLIGHTS
The conversion process and data acquisition are controlled using CS and the serial clock signal, al owing the device to easily interface 1. The AD7490-EP offers up to 1 MSPS throughput rates. with microprocessors or DSPs. The input signal is sampled on the 2. A sequence of channels can be selected, through which the falling edge of CS, and conversion is also initiated at this point. AD7490-EP cycles and converts. 3. There are no pipeline delays associated with the part. The AD7490-EP operates from a single 4.75 V to 5.25 V supply. The VDRIVE function al ows the serial interface to The AD7490-EP uses advanced design techniques to achieve very connect directly to either 3 V or 5 V processor systems low power dissipation at high throughput rates. For maximum independent of VDD. throughput rates, the AD7490-EP consumes just 2.5 mA with 5 V 4. The conversion rate is determined by the serial clock, al owing supplies. the conversion time to be reduced through the serial clock By setting the relevant bits in the control register, the analog input speed increase. The part also features various shutdown range for the part can be selected to be a 0 V to REF modes to maximize power efficiency at lower throughput IN input or a 0 V to 2 × REF rates. Power consumption is 0.5 µA, maximum, when in ful IN input, with either straight binary or twos complement output coding. The AD7490-EP features 16 single-ended analog shutdown. inputs with a channel sequencer to al ow a preprogrammed selec- 5. The part features a standard successive approximation ADC tion of channels to be converted sequential y. The conversion time with accurate control of the sampling instant via a CS input and once off conversion control.
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Document Outline Features Enhanced Product Features Functional Block Diagram General Description Product Highlights Revision History Specifications Timing Specifications Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Outline Dimensions Ordering Guide