Datasheet AD7176-2 (Analog Devices) - 3

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Key Sheet AD7176-2 OPERATING THE AD7176-2 DATA INTERFACE ADC and Interface Mode Configuration
The data interface for the AD7176-2 is The ADC mode register and the interface mode register (see Block A in Figure 3) configure the core peripherals to be used • Performed using a 4- or 3-wire SPI by the AD7176-2 and the mode for the digital interface. • Compatible with SPI, QSPI, MICROWIRE, and DSP
ADC Mode Register
• Al ows a user to both write to and read from the AD7176-2 on the same data bus The ADC mode register is used primarily to set the conversion • mode of the ADC to either continuous or single conversion. Indicates when transferred data is available by bringing the DOUT/RDY signal and the RDY bit in the status register low The user can also select the standby and power-down modes as well as any of the calibration modes. In addition, this register contains the clock source select bits and the internal reference
AD7176-2 (SLAVE)
enable bits.
CS1 Interface Mode Register SCLK
The interface mode register is used to configure the digital
DSP/FPGA DOUT/RDY
interface operation. This register allows the user to control data-word length, CRC enable, and continuous read mode, as
DIN
well as whether status bits are appended to the data that is read.
1CS IS PERMANENTLY TIED LOW IN THE 3-WIRE INTERFACE.
002
DATA MODES (IF CS IS REQUIRED AS A DECODING SIGNAL, IT CAN BE GENERATED FROM A PORT PIN.)
11266- There are three data modes available: continuous conversion Figure 2. AD7176-2 Data Interface, 4-Wire mode, continuous read mode, and single conversion mode.
Table 3. 4-Wire Serial Interface Pin Functions Continuous Conversion Mode (Default) Pin Function
Continuous conversion is the default power-up mode. In this CS1 Selects the ADC (also applicable in systems with mode, the AD7176-2 converts continuously, and the RDY bit in multiple devices on the serial bus). the status register goes low each time a conversion is complete. SCLK Determines when data transfers (either on DIN or If CS is low, the DOUT/RDY line also goes low when a conversion DOUT/RDY) occur. is complete. To read a conversion, the user writes to the DOUT/RDY Accesses data from the on-chip registers. communications register, indicating that the next operation is a Indicates when the transferred data is available. read of the data register. When the data-word has been read from DIN Transfers data into the on-chip registers. the data register, DOUT/RDY goes high. The user can read this 1 CS is permanently tied low in the 3-wire interface. (If CS is required as a register additional times, if required. decoding signal, it can be generated from a port pin.) When several channels are enabled, the ADC automatical y
ACCESSING THE ADC REGISTER MAP
sequences through the enabled channels, performing one conversion on each channel. When al channels have been The communications register controls access to the full register converted, the sequence starts again with the first channel. map of the ADC. This register is an 8-bit write only register. All communication begins by writing to the communications register.
CS
Figure 3 provides an overview of the configuration flow, which is divided into three blocks.
DIN DATA DATA REQUEST REQUEST WRITE TO ADC MODE REGISTER AND INTERFACE MODE REGISTER; A SET UP HIGH LEVEL ADC PERIPHERALS AND INTERFACE DATA DOUT/RDY DATA SET UP CONFIGURATION;
004
B FOUR POSSIBLE ADC SETUPS USING DEDICATED SCLK FILTER, OFFSET, AND GAIN REGISTERS
11266- Figure 4. Continuous Conversion Mode
Continuous Read Mode SELECT THE POSITIVE AND NEGATIVE INPUT FOR EACH C
003
ADC CHANNEL AND MAP EACH CHANNEL TO A SETUP
In continuous read mode, it is not required to write to the 11266- Figure 3. Configuration Flow communications register before reading ADC data; just apply the required number of SCLKs after DOUT/RDY goes low to As Figure 3 shows, three configuration stages are required to set indicate the end of a conversion. When the conversion is read, up the part. Rev. 0 | Page 3 of 6 Document Outline General Description Features and Benefits Key Characteristics Fundamental Specifications Noise Operating the AD7176-2 Data Interface Accessing the ADC Register Map ADC and Interface Mode Configuration ADC Mode Register Interface Mode Register Data Modes Continuous Conversion Mode (Default) Continuous Read Mode Single Conversion Mode Typical Application Diagram Frequently Asked Questions Learn More and Start Designing Compatible Devices Package Diagram Getting Started