Datasheet ADAS3022-EP (Analog Devices) - 9

Enhanced Product ADAS3022-EP Timing Diagrams 500µA IOL 70% VIO 30% VIO tDELAY tDELAY TO SDO 1.4V C 2V OR VIO – 0.5V1 2V OR VIO – 0.5V1 L 50pF 0.8V OR 0.5V2 0.8V OR 0.5V2
03 0
500µA I
-002
1 OH 2V IF VIO > 2.5V; VIO – 0.5V IF VIO < 2.5V.
3- 983
2
598 15
0.8V IF VIO > 2.5V; 0.5V IF VIO < 2.5V.
1 Figure 2. Load Circuit for Digital Interface Timing Figure 3. Voltage Levels for Timing
t t ACQ CYC SOC EOC SOC EOC t t POWER DDC QUIET tDAC UP NOTE 1 NOTE 2 NOTE 1 CONVERSION (n – 1) ACQUISITION (n) CONVERSION (n) ACQUISITION (n + 1) PHASE CONVERSION (n + 1) UNDEFINED UNDEFINED UNDEFINED UNDEFINED UNDEFINED CNV BUSY t NOTE 5 DDCA NOTE 2 tAD NOTE 4 CS X 1 16/32 1 16 SCK NOTE 3 CFG DIN CFG (n + 2) CFG (n + 2) CFG (n + 3) CFG (n + 3) INVALID DATA DATA (n – 1) DATA (n – 1) DATA (n) DATA (n) SDO INVALID INVALID INVALID INVALID INVALID EOC EOC EOC ACQUISITION CONVERSION ACQUISITION CONVERSION ACQUISITION CONVERSION PHASE (n + 2) (n + 2) (n + 3) (n + 3) (n + 4) (n + 4) CNV BUSY CS 1 16 1 16 1 SCK DIN CFG (n + 4) CFG (n + 4) CFG (n + 5) CFG (n + 5) CFG (n + 6) CFG (n + 6) DATA (n + 1) SDO DATA (n + 1) DATA (n + 2) DATA (n + 2) DATA (n + 3) DATA (n + 3) INVALID INVALID NOTES 1. DATA ACCESS CAN OCCUR DURING A CONVERSION ( tDDC), AFTER A CONVERSION (tDAC), OR BOTH DURING AND AFTER A CONVERSION. THE CONVERSION RESULT AND THE CFG REGISTER ARE UPDATED AT THE END OF A CONVERSION (EOC). 2. DATA ACCESS CAN ALSO OCCUR UP TO tDDCA WHILE BUSY IS ACTIVE (SEE THE ADAS3022 DATA SHEET FOR DETAILS). ALL OF THE BUSY TIME CAN BE USED TO ACQUIRE DATA. 3. A TOTAL OF 16 SCK FALLING EDGES IS REQUIRED FOR A CONVERSION RESULT. AN ADDITIONAL 16 EDGES ARE REQUIRED TO READ BACK THE CFG RESULT ASSOCIATED WITH THE CURRENT CONVERSION. 4. CS CAN BE HELD LOW OR CONNECTED TO CNV. CS WITH FULL INDEPENDENT CONTROL IS SHOWN IN THIS FIGURE. 5. FOR OPTIMAL PERFORMANCE, DATA ACCESS SHOULD NOT OCCUR DURING THE SAMPLING EDGE. A MINIMUM TIME
028 83-
OF THE APERTURE DELAY (tAD) SHOULD ELAPSE PRIOR TO DATA ACCESS.
159 Figure 4. General Timing Diagram Rev. 0 | Page 9 of 21 Document Outline Features Enhanced Features Applications General Description Table of Contents Revision History Functional Block Diagram Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Outline Dimensions Ordering Guide