Datasheet ADAS3022-EP (Analog Devices) - 8

ADAS3022-EP Enhanced Product TIMING SPECIFICATIONS
VDDH = 15 V ± 5%, VSSH = −15 V ± 5%, AVDD = DVDD = 5 V ± 5%, VIO = 1.8 V to AVDD, internal reference, VREF = 4.096 V, fS = 1 MSPS unless otherwise noted. All specifications TMIN to TMAX, unless otherwise noted.
Table 3. Parameter Symbol Min Typ Max Unit
Time Between Conversions tCYC Warp Mode,1 CMS = 0 1 1000 µs Normal Mode (Default), CMS = 1 1.1 µs Conversion Time: CNV Rising Edge to Data Available tCONV Warp Mode, CMS = 0 825 ns Normal Mode (Default), CMS = 1 925 1000 ns Auxiliary ADC Input Channel Acquisition Time tACQ 600 ns CNV Pulse Width tCH 10 ns CNV High to Hold Time (Aperture Delay) tAD 2 ns CNV High to Busy Delay tCBD 520 ns Safe Data Access Time During Conversion tDDC 500 ns Quiet Conversion Time (BUSY High) tQUIET Warp Mode, CMS = 0 400 ns Normal Mode (Default), CMS = 1 500 ns Data Access During Quiet Conversion Time tDDCA Warp Mode, CMS = 0 200 ns Normal Mode (Default), CMS = 1 300 ns SCK Period tSCK 15 ns SCK Low Time tSCKL 5 ns SCK High Time tSCKH 5 ns SCK Falling Edge to Data Valid tSDOH 4 ns SCK Falling Edge to Data Valid Delay tSDOD VIO > 4.5 V 12 ns VIO > 3.0 V 18 ns VIO > 2.7 V 24 ns VIO > 2.3 V 25 ns VIO > 1.8 V 37 ns CS/RESET/PD Low to SDO tEN VIO > 4.5 V 15 ns VIO > 3.0 V 16 ns VIO > 2.7 V 18 ns VIO > 2.3 V 23 ns VIO > 1.8 V 28 ns CS/RESET/PD High to SDO High Impedance tDIS 25 ns DIN Valid Setup Time from SCK Rising Edge tDINS 4 ns DIN Valid Hold Time from SCK Rising Edge tDINH 4 ns CNV Rising to CS tCCS 5 ns RESET/PD High Pulse tRH 5 ns 1 Exceeding the maximum time has an effect on the accuracy of the conversion. Rev. 0 | Page 8 of 21 Document Outline Features Enhanced Features Applications General Description Table of Contents Revision History Functional Block Diagram Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Outline Dimensions Ordering Guide