Datasheet ADAR7251 (Analog Devices) - 2
| Hersteller | Analog Devices |
| Beschreibung | 4-Channel, 16-Bit, Continuous Time Data Acquisition ADC |
| Seiten / Seite | 72 / 2 — ADAR7251. Data Sheet. TABLE OF CONTENTS |
| Dateiformat / Größe | PDF / 4.4 Mb |
| Dokumentensprache | Englisch |
ADAR7251. Data Sheet. TABLE OF CONTENTS
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ADAR7251 Data Sheet TABLE OF CONTENTS
Features .. 1 PLL Control Register ... 38 Applications ... 1 PLL Status Register ... 38 General Description ... 1 Master Enable Switch Register ... 39 Revision History ... 3 ADC Enable Register ... 39 Functional Block Diagram .. 4 Power Enable Register ... 40 Specifications ... 5 Clear the ASIL errors Register .. 41 Analog Channel .. 5 Selects Which Errors to Mask Register ... 42 Digital Input/Output .. 6 ASIL Error Flag Register ... 43 Power Supply ... 7 ASIL Error Code Register ... 43 Digital Filter .. 8 CRC Value, Bits[7:0] Register ... 44 SPI Port Timing .. 8 CRC Value Register .. 44 Serial/Peripheral Parallel Interface (PPI) Port Timing.. 8 Start Calculating the CRC Value of the Register Map Content Absolute Maximum Ratings .. 11 Register .. 45 Thermal Resistance .. 11 Register Map CRC Calculation Done Register .. 45 ESD Caution .. 11 Register Map CRC Value, Bits[7:0] Register ... 45 Pin Configuration and Function Descriptions ... 12 Register Map CRC Value, Bits[15:8] Register ... 46 Typical Performance Characteristics ... 14 Low Noise Amplifier Gain Control Register .. 46 Terminology .. 17 Programmable Gain Amplifier Gain Control Register ... 47 Theory of Operation .. 18 Signal Path for ADC 1 Through ADC 4 Register .. 48 Low Speed Ramp Radar Analog Front End .. 18 Decimator Rate Control Register ... 49 Main Channel Overview ... 18 High Pass Filter Control Register ... 50 Σ-Δ Modulation and Digital Filtering ... 18 DAQ Mode Control Register .. 51 Differential Input Configuration .. 19 Decimator Truncate Control Register ... 52 Equalizer (EQ) .. 19 Serial Output Port Control Register .. 52 Using LNA/PGA, EQ, or the Input Capacitor .. 20 Parallel Port Control Register ... 53 Reference ... 20 ADC Digital Output Mode Register .. 54 Auxiliary ADC .. 20 Auxiliary ADC Read Value Registers .. 54 Power Supply ... 21 Auxiliary ADC Sample Rate Selection Register ... 55 LDO .. 21 Auxiliary ADC Mode Register ... 56 Clock Requirements ... 21 MPx Pin Modes Registers ... 56 Crystal Oscillator .. 21 MP Write Value Registers .. 58 PLL ... 21 MP Read Value Registers... 58 GPIO .. 23 SPI_CLK Pin Drive Strength and Slew Rate Register ... 59 ADC Data Port ... 23 SPI_MISO Pin Drive Strength and Slew Rate Register ... 60 PCB Layout Guidelines .. 33 SPI_SS Pin Drive Strength and Slew Rate Register ... 60 Register Summary .. 34 SPI_MOSI Pin Drive Strength and Slew Rate Register ... 61 Register Details ... 37 ADDR15 Pin Drive Strength and Slew Rate Register ... 62 Clock Control Register .. 37 FAULT Pin Drive Strength and Slew Rate Register ... 62 PLL Denominator Register ... 37 FS_ADC Pin Drive Strength and Slew Rate Register .. 63 PLL Numerator Register .. 37 CONV_START Pin Drive Strength and Slew Rate Register ... 64 Rev. 0 | Page 2 of 72 Document Outline Features Applications General Description Revision History Functional Block Diagram Specifications Analog Channel Digital Input/Output Power Supply Digital Filter SPI Port Timing Serial/Peripheral Parallel Interface (PPI) Port Timing Timing Diagrams Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Terminology Theory of Operation Low Speed Ramp Radar Analog Front End Main Channel Overview Σ-∆ Modulation and Digital Filtering Differential Input Configuration High-Pass Filter (HPF) Low-Pass Filter (LPF) Input Routing Equalizer (EQ) Using LNA/PGA, EQ, or the Input Capacitor Reference Auxiliary ADC Power Supply LDO Clock Requirements Crystal Oscillator PLL Integer Mode Fractional Mode PLL Lock Acquisition GPIO ADC Data Port ADC Serial Mode ADC Serial Master Mode ADC Serial Master Mode with ADC Serial Slave ADC PPI (Byte Wide Mode) ADC PPI Nibble Wide Mode DAQ Mode Using Multiple ADAR7251 Devices for Systems with More Than Four Channels Device Address R/ Register Address Data Bytes CRC PCB Layout Guidelines Register Summary Register Details Clock Control Register PLL Denominator Register PLL Numerator Register PLL Control Register PLL Status Register Master Enable Switch Register ADC Enable Register Power Enable Register Clear the ASIL errors Register Selects Which Errors to Mask Register ASIL Error Flag Register ASIL Error Code Register CRC Value, Bits[7:0] Register CRC Value Register Start Calculating the CRC Value of the Register Map Content Register Register Map CRC Calculation Done Register Register Map CRC Value, Bits[7:0] Register Register Map CRC Value, Bits[15:8] Register Low Noise Amplifier Gain Control Register Programmable Gain Amplifier Gain Control Register Signal Path for ADC 1 Through ADC 4 Register Decimator Rate Control Register High Pass Filter Control Register DAQ Mode Control Register Decimator Truncate Control Register Serial Output Port Control Register Parallel Port Control Register ADC Digital Output Mode Register Auxiliary ADC Read Value Registers Auxiliary ADC Sample Rate Selection Register Auxiliary ADC Mode Register MPx Pin Modes Registers MP Write Value Registers MP Read Value Registers SPI_CLK Pin Drive Strength and Slew Rate Register SPI_MISO Pin Drive Strength and Slew Rate Register Pin Drive Strength and Slew Rate Register SPI_MOSI Pin Drive Strength and Slew Rate Register ADDR15 Pin Drive Strength and Slew Rate Register Pin Drive Strength and Slew Rate Register FS_ADC Pin Drive Strength and Slew Rate Register Pin Drive Strength and Slew Rate Register SCLK_ADC Pin Drive Strength and Slew Rate Register ADC_DOUTx Pins Drive Strength and Slew Rate Registers DATA_READY Pin Drive Strength and Slew Rate Register XTAL Enable and Drive Register ADC Test Register Digital Filter Sync Enable Register CRC Enable/Disable Register Typical Application Circuit Outline Dimensions Ordering Guide Automotive Products
ADAR7251 Data Sheet TABLE OF CONTENTS
Features .. 1 PLL Control Register ... 38 Applications ... 1 PLL Status Register ... 38 General Description ... 1 Master Enable Switch Register ... 39 Revision History ... 3 ADC Enable Register ... 39 Functional Block Diagram .. 4 Power Enable Register ... 40 Specifications ... 5 Clear the ASIL errors Register .. 41 Analog Channel .. 5 Selects Which Errors to Mask Register ... 42 Digital Input/Output .. 6 ASIL Error Flag Register ... 43 Power Supply ... 7 ASIL Error Code Register ... 43 Digital Filter .. 8 CRC Value, Bits[7:0] Register ... 44 SPI Port Timing .. 8 CRC Value Register .. 44 Serial/Peripheral Parallel Interface (PPI) Port Timing.. 8 Start Calculating the CRC Value of the Register Map Content Absolute Maximum Ratings .. 11 Register .. 45 Thermal Resistance .. 11 Register Map CRC Calculation Done Register .. 45 ESD Caution .. 11 Register Map CRC Value, Bits[7:0] Register ... 45 Pin Configuration and Function Descriptions ... 12 Register Map CRC Value, Bits[15:8] Register ... 46 Typical Performance Characteristics ... 14 Low Noise Amplifier Gain Control Register .. 46 Terminology .. 17 Programmable Gain Amplifier Gain Control Register ... 47 Theory of Operation .. 18 Signal Path for ADC 1 Through ADC 4 Register .. 48 Low Speed Ramp Radar Analog Front End .. 18 Decimator Rate Control Register ... 49 Main Channel Overview ... 18 High Pass Filter Control Register ... 50 Σ-Δ Modulation and Digital Filtering ... 18 DAQ Mode Control Register .. 51 Differential Input Configuration .. 19 Decimator Truncate Control Register ... 52 Equalizer (EQ) .. 19 Serial Output Port Control Register .. 52 Using LNA/PGA, EQ, or the Input Capacitor .. 20 Parallel Port Control Register ... 53 Reference ... 20 ADC Digital Output Mode Register .. 54 Auxiliary ADC .. 20 Auxiliary ADC Read Value Registers .. 54 Power Supply ... 21 Auxiliary ADC Sample Rate Selection Register ... 55 LDO .. 21 Auxiliary ADC Mode Register ... 56 Clock Requirements ... 21 MPx Pin Modes Registers ... 56 Crystal Oscillator .. 21 MP Write Value Registers .. 58 PLL ... 21 MP Read Value Registers... 58 GPIO .. 23 SPI_CLK Pin Drive Strength and Slew Rate Register ... 59 ADC Data Port ... 23 SPI_MISO Pin Drive Strength and Slew Rate Register ... 60 PCB Layout Guidelines .. 33 SPI_SS Pin Drive Strength and Slew Rate Register ... 60 Register Summary .. 34 SPI_MOSI Pin Drive Strength and Slew Rate Register ... 61 Register Details ... 37 ADDR15 Pin Drive Strength and Slew Rate Register ... 62 Clock Control Register .. 37 FAULT Pin Drive Strength and Slew Rate Register ... 62 PLL Denominator Register ... 37 FS_ADC Pin Drive Strength and Slew Rate Register .. 63 PLL Numerator Register .. 37 CONV_START Pin Drive Strength and Slew Rate Register ... 64 Rev. 0 | Page 2 of 72 Document Outline Features Applications General Description Revision History Functional Block Diagram Specifications Analog Channel Digital Input/Output Power Supply Digital Filter SPI Port Timing Serial/Peripheral Parallel Interface (PPI) Port Timing Timing Diagrams Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Terminology Theory of Operation Low Speed Ramp Radar Analog Front End Main Channel Overview Σ-∆ Modulation and Digital Filtering Differential Input Configuration High-Pass Filter (HPF) Low-Pass Filter (LPF) Input Routing Equalizer (EQ) Using LNA/PGA, EQ, or the Input Capacitor Reference Auxiliary ADC Power Supply LDO Clock Requirements Crystal Oscillator PLL Integer Mode Fractional Mode PLL Lock Acquisition GPIO ADC Data Port ADC Serial Mode ADC Serial Master Mode ADC Serial Master Mode with ADC Serial Slave ADC PPI (Byte Wide Mode) ADC PPI Nibble Wide Mode DAQ Mode Using Multiple ADAR7251 Devices for Systems with More Than Four Channels Device Address R/ Register Address Data Bytes CRC PCB Layout Guidelines Register Summary Register Details Clock Control Register PLL Denominator Register PLL Numerator Register PLL Control Register PLL Status Register Master Enable Switch Register ADC Enable Register Power Enable Register Clear the ASIL errors Register Selects Which Errors to Mask Register ASIL Error Flag Register ASIL Error Code Register CRC Value, Bits[7:0] Register CRC Value Register Start Calculating the CRC Value of the Register Map Content Register Register Map CRC Calculation Done Register Register Map CRC Value, Bits[7:0] Register Register Map CRC Value, Bits[15:8] Register Low Noise Amplifier Gain Control Register Programmable Gain Amplifier Gain Control Register Signal Path for ADC 1 Through ADC 4 Register Decimator Rate Control Register High Pass Filter Control Register DAQ Mode Control Register Decimator Truncate Control Register Serial Output Port Control Register Parallel Port Control Register ADC Digital Output Mode Register Auxiliary ADC Read Value Registers Auxiliary ADC Sample Rate Selection Register Auxiliary ADC Mode Register MPx Pin Modes Registers MP Write Value Registers MP Read Value Registers SPI_CLK Pin Drive Strength and Slew Rate Register SPI_MISO Pin Drive Strength and Slew Rate Register Pin Drive Strength and Slew Rate Register SPI_MOSI Pin Drive Strength and Slew Rate Register ADDR15 Pin Drive Strength and Slew Rate Register Pin Drive Strength and Slew Rate Register FS_ADC Pin Drive Strength and Slew Rate Register Pin Drive Strength and Slew Rate Register SCLK_ADC Pin Drive Strength and Slew Rate Register ADC_DOUTx Pins Drive Strength and Slew Rate Registers DATA_READY Pin Drive Strength and Slew Rate Register XTAL Enable and Drive Register ADC Test Register Digital Filter Sync Enable Register CRC Enable/Disable Register Typical Application Circuit Outline Dimensions Ordering Guide Automotive Products