Datasheet ADAR7251 (Analog Devices)

4-Channel, 16-Bit, Continuous Time Data Acquisition ADC Data Sheet ADAR7251 FEATURES GENERAL DESCRIPTION Low noise: 2.4 nV/√Hz input referred voltage noise at
The ADAR7251 is a 16-bit, 4-channel, simultaneous sampling
maximum gain setting
analog-to-digital converter (ADC) designed especially for
Wide input signal bandwidth: 500 kHz at 1.2 MSPS sample
applications such as automotive LSR-FMCW or FSK-FMCW
rate, 16-bit resolution
radar systems. Each of the four channels contains a low noise
Additional sample rates supported: 300 kSPS, 450 kSPS,
amplifier (LNA), a programmable gain amplifier (PGA), an
600 kSPS, 900 kSPS, and 1.8 MSPS
equalizer, a multibit Σ-Δ ADC, and a decimation filter.
4 differential simultaneous sampling channels
The front-end circuitry is designed to allow direct connection
No active antialiasing filter required
to an MMIC output with few external passive components. The
LNA and PGA with 45 dB gain range in 6 dB steps
ADAR7251 eliminates the need for a high order antialiasing
Selectable equalizer
filter, driver op amps, and external bipolar supplies. The
Flexible data port supports serial or parallel mode
ADAR7251 also offers precise channel-to-channel drift
Supports FSK mode for FMCW radar systems
matching.
On-chip 1.5 V reference Internal oscillator/PLL input: 16 MHz to 54 MHz
The ADAR7251 features an on-chip phase-locked loop (PLL)
High speed serial data interface
that allows a range of clock frequencies for flexibility in the system.
SPI control
The CONV_START input and DATA_READY output signals
2 general-purpose inputs/outputs
synchronize the ADC with an external ramp for applications such
48-lead LFCSP_SS package
as FSK-FMCW radar.
Temperature range: −40°C to +125°C
The ADAR7251 supports serial and parallel interfaces at
Single supply operation of 3.3 V
programmable sample rates from 300 kSPS to 1.8 MSPS, as well
Qualified for automotive applications
as easy connections to digital signal processors (DSPs) and
APPLICATIONS
microcontroller units (MCUs) in the system.
Automotive LSR systems Data acquisition systems Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2014 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
Document Outline Features Applications General Description Revision History Functional Block Diagram Specifications Analog Channel Digital Input/Output Power Supply Digital Filter SPI Port Timing Serial/Peripheral Parallel Interface (PPI) Port Timing Timing Diagrams Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Terminology Theory of Operation Low Speed Ramp Radar Analog Front End Main Channel Overview Σ-∆ Modulation and Digital Filtering Differential Input Configuration High-Pass Filter (HPF) Low-Pass Filter (LPF) Input Routing Equalizer (EQ) Using LNA/PGA, EQ, or the Input Capacitor Reference Auxiliary ADC Power Supply LDO Clock Requirements Crystal Oscillator PLL Integer Mode Fractional Mode PLL Lock Acquisition GPIO ADC Data Port ADC Serial Mode ADC Serial Master Mode ADC Serial Master Mode with ADC Serial Slave ADC PPI (Byte Wide Mode) ADC PPI Nibble Wide Mode DAQ Mode Using Multiple ADAR7251 Devices for Systems with More Than Four Channels Device Address R/ Register Address Data Bytes CRC PCB Layout Guidelines Register Summary Register Details Clock Control Register PLL Denominator Register PLL Numerator Register PLL Control Register PLL Status Register Master Enable Switch Register ADC Enable Register Power Enable Register Clear the ASIL errors Register Selects Which Errors to Mask Register ASIL Error Flag Register ASIL Error Code Register CRC Value, Bits[7:0] Register CRC Value Register Start Calculating the CRC Value of the Register Map Content Register Register Map CRC Calculation Done Register Register Map CRC Value, Bits[7:0] Register Register Map CRC Value, Bits[15:8] Register Low Noise Amplifier Gain Control Register Programmable Gain Amplifier Gain Control Register Signal Path for ADC 1 Through ADC 4 Register Decimator Rate Control Register High Pass Filter Control Register DAQ Mode Control Register Decimator Truncate Control Register Serial Output Port Control Register Parallel Port Control Register ADC Digital Output Mode Register Auxiliary ADC Read Value Registers Auxiliary ADC Sample Rate Selection Register Auxiliary ADC Mode Register MPx Pin Modes Registers MP Write Value Registers MP Read Value Registers SPI_CLK Pin Drive Strength and Slew Rate Register SPI_MISO Pin Drive Strength and Slew Rate Register Pin Drive Strength and Slew Rate Register SPI_MOSI Pin Drive Strength and Slew Rate Register ADDR15 Pin Drive Strength and Slew Rate Register Pin Drive Strength and Slew Rate Register FS_ADC Pin Drive Strength and Slew Rate Register Pin Drive Strength and Slew Rate Register SCLK_ADC Pin Drive Strength and Slew Rate Register ADC_DOUTx Pins Drive Strength and Slew Rate Registers DATA_READY Pin Drive Strength and Slew Rate Register XTAL Enable and Drive Register ADC Test Register Digital Filter Sync Enable Register CRC Enable/Disable Register Typical Application Circuit Outline Dimensions Ordering Guide Automotive Products