Datasheet A4975 (Allegro) - 9

A4975 Full-Bridge PWM Microstepping Motor Driver Mixed Current Decay Mode.
If VPFD is between 1.1 V With increasing values of tOFF, switching losses will decrease, and 3.1 V, the device will be in a mixed current decay mode. low-level load-current regulation will improve, EMI will be Mixed decay mode allows the user to achieve good current reduced, the PWM frequency will decrease, and ripple current regulation with a minimum amount of ripple current and motor/ will increase. A value of tOFF can be chosen for optimization driver losses by selecting the minimum percentage of fast decay of these parameters. For applications where audible noise is a required for their application (see also the Stepper Motor Appli- concern, typical values of tOFF are chosen to be in the range of cations section). 15 to 35 µs. As in fast current decay mode, mixed decay starts with the sink
RC Blanking.
In addition to determining the fixed off-time of and source drivers disabled and the opposite pair turned on after the PWM control circuit, the CT component sets the comparator the load current reaches ITRIP. When the voltage at the RC termi- blanking time. This function blanks the output of the current- nal decays to a value below VPFD, the sink drivers are re-enabled, sense comparator when the outputs are switched by the internal placing the device in slow current decay mode for the remainder current-control circuitry (or by the PHASE input, or when the of the fixed off-time (figure 2). The percentage of fast decay device is enabled with the DAC data inputs). The comparator (PFD) is user determined by VPFD or two external resistors. output is blanked to prevent false overcurrent detections due to PFD = 100 ln (0.6[R reverse recovery currents of the clamp diodes, and/or switching 1+R2]/R2) transients related to distributed capacitance in the load. where: V During internal PWM operation, at the end of the tOFF time, the CC comparator’s output is blanked and CT begins to be charged from approximately 0.22 × V R CC by an internal current source of 1 approximately 1 mA. The comparator output remains blanked until the voltage on C PFD T reaches approximately 0.6 × VCC. The blanking time, tBLANK, can be calculated as: R2 tBLANK = RTCT ln (RT/[RT – 3 kΩ]). When a transition of the PHASE input occurs, CT is discharged Dwg. EP-062-1 to near ground during the crossover delay time (the crossover delay time is present to prevent simultaneous conduction of the
Fixed Off-Time.
The internal PWM current control circuitry source and sink drivers). After the crossover delay, CT is charged uses a one-shot to control the time the driver(s) remain(s) off. by an internal current source of approximately 1 mA. The com- The one-shot off-time, tOFF, is determined by the selection of parator output remains blanked until the voltage on CT reaches an external resistor (RT) and capacitor (CT) connected from the approximately 0.6 × VCC. RC timing terminal to ground. The off-time, over a range of Similarly, when the device is disabled, via the DAC data inputs, values of CT = 470 pF to 1500 pF and RT = 12 kΩ to 100 kΩ, is C approximated by: T is discharged to near ground. When the device is re-enabled, CT is charged by an internal current source of approximately 1 tOFF ≈ RTCT. mA. The comparator output remains blanked until the voltage on C When the load current is increasing, but has not yet reached the T reaches approximately 0.6 × VCC. The blanking time, tBLANK, can be calculated as: sense-current comparator threshold (ITRIP), the voltage on the RC terminal is approximately 0.6 × VCC. When ITRIP is reached, the tBLANK = RTCT ln ([RT – 1.1 kΩ]/RT – 3 kΩ). PWM latch is reset by the current-sense comparator and the voltage The minimum recommended value for C on the RC terminal will decay until it reaches approximately 0.22 × T is 470 pF ± 5 %. This value ensures that the blanking time is sufficient to avoid false VCC. The PWM latch is then set, thereby re-enabling the driver(s) trips of the comparator under normal operating conditions. For and allowing load current to increase again. The PWM cycle optimal regulation of the load current, this value for C repeats, maintaining the peak load current at the desired value. T is recom- mended and the value of RT can be sized to determine tOFF. Allegro MicroSystems, LLC 9 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com