Datasheet A4975 (Allegro)
| Hersteller | Allegro |
| Beschreibung | Full-Bridge PWM Microstepping Motor Driver |
| Seiten / Seite | 14 / 1 — A4975. Full-Bridge PWM Microstepping Motor Driver. FEATURES AND BENEFITS. … |
| Dateiformat / Größe | PDF / 842 Kb |
| Dokumentensprache | Englisch |
A4975. Full-Bridge PWM Microstepping Motor Driver. FEATURES AND BENEFITS. DESCRIPTION. PACKAGES:. Functional Block Diagram
Modelllinie für dieses Datenblatt
Textversion des Dokuments
A4975 Full-Bridge PWM Microstepping Motor Driver FEATURES AND BENEFITS DESCRIPTION
▪ ±1.5 A continuous output current The A4975 is designed to drive one winding of a bipolar ▪ 50 V output voltage rating stepper motor in a microstepping mode. The outputs are ▪ Internal PWM current control rated for continuous output currents to ±1.5 A and operating ▪ 3-bit nonlinear DAC voltages to 50 V. Internal pulse width modulated (PWM) current ▪ Fast, mixed fast/slow, and slow current decay modes control combined with an internal three-bit nonlinear digital- ▪ Internal thermal shutdown circuitry to-analog converter allows the motor current to be controlled ▪ Crossover-current and UVLO protection in full-, half-, quarter-, or eighth-step (microstepping) modes. Nonlinear increments minimize the number of control lines necessary for microstepping. Microstepping provides increased step resolution, and reduces torque variations and resonance
PACKAGES:
problems at low speed. Internal circuitry determines whether the PWM current control circuitry operates in a slow (recirculating) current decay mode, fast (regenerative) current decay mode, or in a mixed current decay mode in which the off-time is divided into a period of fast current decay and with the remainder of the fixed off-time spent in slow current decay. The combination of user-selectable current-sensing resistor and reference voltage, digitally selected output current ratio, and slow, fast, or mixed current decay modes Package B, 16-pin DIP Package LB, 16-pin SOIC provides users with a broad, variable range of motor control. with exposed tabs with internally fused pins Not to scale Continued on the next page…
Functional Block Diagram
C T A T B U U LOGI SUPPLY O O LOAD SUPPLY 6 10 15 16 PHASE VCC 7 VBB GROUND 4 5 UVLO 12 & TSD 13 BLANKING CURRENT-SENSE SENSE MIXED-DECAY PWM LATCH GATE COMPARATOR 11 COMPARATOR + PFD 1 + R – – Q S BLANKING ÷5 D/A DISABLE R V + – S CC RC VTH 3 VCC VCC VCC CT 47 kΩ (typ) 47 kΩ (typ) 47 kΩ (typ) RT 2 8 9 14 F 2 1 0 RE D D D 4975-DS, Rev. 5 January 29, 2019 MCO-0000193
▪ ±1.5 A continuous output current The A4975 is designed to drive one winding of a bipolar ▪ 50 V output voltage rating stepper motor in a microstepping mode. The outputs are ▪ Internal PWM current control rated for continuous output currents to ±1.5 A and operating ▪ 3-bit nonlinear DAC voltages to 50 V. Internal pulse width modulated (PWM) current ▪ Fast, mixed fast/slow, and slow current decay modes control combined with an internal three-bit nonlinear digital- ▪ Internal thermal shutdown circuitry to-analog converter allows the motor current to be controlled ▪ Crossover-current and UVLO protection in full-, half-, quarter-, or eighth-step (microstepping) modes. Nonlinear increments minimize the number of control lines necessary for microstepping. Microstepping provides increased step resolution, and reduces torque variations and resonance
PACKAGES:
problems at low speed. Internal circuitry determines whether the PWM current control circuitry operates in a slow (recirculating) current decay mode, fast (regenerative) current decay mode, or in a mixed current decay mode in which the off-time is divided into a period of fast current decay and with the remainder of the fixed off-time spent in slow current decay. The combination of user-selectable current-sensing resistor and reference voltage, digitally selected output current ratio, and slow, fast, or mixed current decay modes Package B, 16-pin DIP Package LB, 16-pin SOIC provides users with a broad, variable range of motor control. with exposed tabs with internally fused pins Not to scale Continued on the next page…
Functional Block Diagram
C T A T B U U LOGI SUPPLY O O LOAD SUPPLY 6 10 15 16 PHASE VCC 7 VBB GROUND 4 5 UVLO 12 & TSD 13 BLANKING CURRENT-SENSE SENSE MIXED-DECAY PWM LATCH GATE COMPARATOR 11 COMPARATOR + PFD 1 + R – – Q S BLANKING ÷5 D/A DISABLE R V + – S CC RC VTH 3 VCC VCC VCC CT 47 kΩ (typ) 47 kΩ (typ) 47 kΩ (typ) RT 2 8 9 14 F 2 1 0 RE D D D 4975-DS, Rev. 5 January 29, 2019 MCO-0000193