Datasheet ADuM4136 (Analog Devices) - 3

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Data Sheet ADuM4136 SPECIFICATIONS ELECTRICAL CHARACTERISTICS
Low-side voltages are referenced to VSS1. High-side voltages are referenced to GND2; 2.5 V ≤ VDD1 ≤ 6 V, 12 V ≤ VDD2 ≤ 35 V, and TJ = −40°C to +125°C. All minimum/maximum specifications apply over the entire recommended operating range, unless otherwise noted. All typical specifications are at TJ = 25°C, VDD1 = 5.0 V, VSS2 = 0 V, and VDD2 = 15 V.
Table 1. Parameter Symbol Min Typ Max Unit Test Conditions/Comments
DC SPECIFICATIONS High-Side Power Supply Input Voltage VDD2 VDD2 12 35 V VDD2 − VSS2 ≤ 35 V VSS2 VSS2 −15 0 V Input Current, Quiescent Ready high VDD2 IDD2 (Q) 3.62 4.49 mA VSS2 ISS2 (Q) 4.82 6.21 mA Logic Supply VDD1 Input Voltage VDD1 2.5 6 V Input Current IDD1 Output Low 1.78 2.17 mA Output signal low Output High 4.78 5.89 mA Output signal high Logic Inputs (VI+, VI−, RESET) Input Current (VI+, VI− Only) II −1 +0.01 +1 μA Input Voltage Logic High VIH 0.7 × VDD1 V 2.5 V ≤ VDD1 − VSS1 ≤ 5 V 3.5 V VDD1 − VSS1 > 5 V Logic Low VIL 0.3 × VDD1 V 2.5 V ≤ VDD1 − VSS1 ≤ 5 V 1.5 V VDD1 − VSS1 > 5 V RESET Internal Pull-Down RRESET_PD 300 kΩ Undervoltage Lockout (UVLO) VDD1 Positive Going Threshold VVDD1UV+ 2.43 2.49 V Negative Going Threshold VVDD1UV− 2.29 2.34 V Hysteresis VVDD1UVH 0.09 V VDD2 Positive Going Threshold VVDD2UV+ 11.6 12.0 V Negative Going Threshold VVDD2UV− 10.4 11.2 V Hysteresis VVDD2UVH 0.4 V FAULT Pull-Down FET Resistance RFAULT_PD_FET 11 50 Ω Tested at 5 mA READY Pull-Down FET Resistance RRDY_PD_FET 11 50 Ω Tested at 5 mA Desaturation (DESAT) Desaturation Detect Comparator Voltage VDESAT, TH 8.66 9.2 9.57 V Internal Current Source IDESAT_SRC 466 537 592 μA Thermal Shutdown (TSD) TSD Positive Edge TTSD_POS 155 °C TSD Hysteresis TTSD_HYST 20 °C Internal NMOS Gate On Resistance RDSON_N 322 625 mΩ Tested at 250 mA 325 625 mΩ Tested at 1 A Internal PMOS Gate On Resistance RDSON_P 475 975 mΩ Tested at 250 mA 480 975 mΩ Tested at 1 A Soft Shutdown NMOS On Resistance RDSON_FAULT 10.4 22 Ω Tested at 250 mA Peak Current 4.61 A VDD2 = 12 V, 2 Ω gate resistance SWITCHING SPECIFICATIONS Pulse Width1 PW 50 ns C 2 2 L = 2 nF, VDD2 = 15 V, RGON = RGOFF = 3.9 Ω RESET Debounce tDEB_RESET 500 615 700 ns Rev. 0 | Page 3 of 16 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Electrical Characteristics Package Characteristics Regulatory Information Insulation and Safety Related Specifications DIN V VDE V 0884-10 (VDE V 0884-10) Insulation Characteristics Recommended Operating Conditions Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performanace Characteristics Applications Information PCB Layout Propagation Delay Related Parameters Protection Features Fault Reporting Desaturation Detection Thermal Shutdown Undervoltage Lockout (UVLO) Faults READY Pin Pin Pin VI+ and VI− Operation Gate Resistance Selection Power Dissipation DC Correctness and Magnetic Field Immunity Insulation Lifetime Surface Tracking Insulation Wear Out Calculation and Use of Parameters Example Typical Application Outline Dimensions Ordering Guide